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參數(shù)資料
| 型號(hào)： | 1200 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC20 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, QLP-20 |
| 文件頁數(shù)： | 11/70頁 |
| 文件大?。?/td> | 841K |
| 代理商： | 1200 |
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Chipcon
SmartRF CC1100
Chipcon AS
SmartRF
CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
Page 19 of 68
The last four bits (3:0) in the status byte con-
tains FIFO_BYTES_AVAILABLE. For read
operations,
the
field contains the number of bytes available for
reading from the RX FIFO. For write
operations,
the
field contains the number of bytes free for
writing
into
the
TX
FIFO.
When
, 15 or more
bytes are available/free.
18.2
Register Access
The configuration registers on the
CC1100 are
located on SPI addresses from 0x00 to 0x2F.
registers. The detailed description of each
register is found in Section 37.1, starting on
page 45. All configuration registers can be
both written to and read. The read/write bit
controls if the register should be written to or
read. When writing to registers, the status byte
is sent on the SO pin each time a data byte to
be written is transmitted on the SI pin.
Registers with consecutive addresses can be
accessed in an efficient way by setting the
burst bit in the address header. The address
sets the start address in an internal address
counter. This counter is incremented by one
each new byte (every 8 clock pulses). The
burst access is either a read or a write access
and must be terminated by setting CSn high.
For register addresses in the range 0x30-
0x3D, the “burst” bit is used to select between
status registers and command strobes (see
below). The status registers can only be read.
Burst read is not available for status registers,
so they must be read one at a time.
18.3
Command Strobes
Command Strobes may be viewed as single
byte instructions to
CC1100. By addressing a
Command Strobe register, internal sequences
will be started. These commands are used to
disable the crystal oscillator, enable receive
mode, enable wake-on-radio etc. The 14
command strobes are listed in Table 28 on
page 41.
The command strobe registers are accessed
in the same way as for a register write
operation, but no data is transferred. That is,
only the R/W bit (set to 0), burst access (set to
0) and the six address bits (in the range 0x30
through 0x3D) are written. A command strobe
may be followed by any other SPI access
without pulling CSn high. The command
strobes are executed immediately, with the
exception of the SPWD and the SXOFF strobes
that are executed when CSn goes high.
18.4
FIFO Access
The 64-byte TX FIFO and the 64-byte RX
FIFO
are
accessed
through
the
0x3F
addresses. When the read/write bit is zero, the
TX FIFO is accessed, and the RX FIFO is
accessed when the read/write bit is one.
The TX FIFO is write-only, while the RX FIFO
is read-only.
The burst bit is used to determine if FIFO
access is single byte or a burst access. The
single byte access method expects address
with burst bit set to zero and one data byte.
After the data byte a new address is expected;
hence, CSn can remain low. The burst access
method expects one address byte and then
consecutive data bytes until terminating the
access by setting CSn high.
The following header bytes access the FIFOs:
0x3F: Single byte access to TX FIFO
0x7F: Burst access to TX FIFO
0xBF: Single byte access to RX FIFO
0xFF: Burst access to RX FIFO
When writing to the TX FIFO, the status byte
(see Section 18.1) is output for each new data
byte on SO, as shown in Figure 6. This status
byte can be used to detect TX FIFO underflow
while writing data to the TX FIFO. Note that
the status byte contains the number of bytes
free before writing the byte in progress to the
TX FIFO. When the last byte that fits in the TX
FIFO is transmitted to the SI pin, the status
byte received concurrently on the SO pin will
indicate that one byte is free in the TX FIFO.
The transmit FIFO may be flushed by issuing a
command strobe. Similarly, a SFRX
command strobe will flush the receive FIFO.
Both FIFOs are cleared when going to the
SLEEP state.
18.5
PATABLE Access
The 0x3E address is used to access the
PATABLE
, which is used for selecting PA
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