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參數(shù)資料
| 型號(hào)： | 1048C |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | Shielded Paired Cable; Number of Conductors:10; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyethylene; Number of Pairs:5; Leaded Process Compatible:Yes; Drop Ship:Yes RoHS Compliant: Yes |
| 中文描述： | 在系統(tǒng)可編程高密度可編程邏輯器件 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 185K |
| 代理商： | 1048C |
Specifications
ispLSI 1048C/883
8
ispLSI 1048C/883 Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
4 PT Bypass
#36
20 PT
XOR Delays
Control
PTs
#447
LDelay
#34, 35
Input
RST
DiClock
I/O Pin
(Input)
Y0
Y1,2,3
D
Q
GRP 4
#32
GLB Reg Bypass
#40
ORP Bypass
#49
D
Q
RST
RE
OE
CK
I/O Reg Bypass
#24
I/O Cell
ORP
GLB
GRP
I/O Cell
#25 - 29
#37, 38, 39
#57, 58
#54
#48
Reset
Ded. In
#30
#59
#59
#
41, 42,
#51, 52
#50
GOE0, 1
0491A/48
#53
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
t
su
= Logic + Reg su - Clock (min)
=
(
t
iobp +
t
grp4 +
t
20ptxor
)
+
(
t
gsu
) - (
t
iobp +
t
grp4 +
t
ptck(min)
)
=
(
#24 + #32 + #38
)
+
(
#41
) - (
#24 + #32 + #47
)
8.0 ns= (4.3 + 6.7 + 7.5) + (3.9) - (4.3 + 6.7 + 3.4)
t
h
= Clock (max) + Reg h - Logic
=
(
t
iobp +
t
grp4 +
t
ptck(max)
)
+
(
t
gh
) - (
t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#24 + #32 + #47
)
+
(
#42
) - (
#24 + #32 + #38
)
8.0 ns= (4.3 + 6.7 + 8.2) + (7.3) - (4.3 + 6.7 + 7.5)
t
co
= Clock (max) + Reg co + Output
=
(
t
iobp +
t
grp4 +
t
ptck(max)
)
+
(
t
gco
)
+
(
t
orp +
t
ob
)
=
(
#24 + #32 + #47
)
+
(
#43
)
+
(
#48 + #50
)
32.8 ns = (4.3 + 6.7 + 8.2) + (7.3) + (3.4 + 2.9)
Derivations of
t
su,
t
h and
t
co from the Clock GLB
1
t
su
= Logic + Reg su - Clock (min)
=
(
t
iobp +
t
grp4 +
t
20ptxor
)
+
(
t
gsu
) - (
t
gy0(min) +
t
gco +
t
gcp(min)
)
=
(
#24 + #32 + #38
)
+
(
#41
) - (
#54 + #43 + #56
)
10.1 ns= (4.3 + 6.7 + 7.5) + (3.9) - (7.4 + 2.3 + 2.6)
t
h
= Clock (max) + Reg h - Logic
=
(
t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(
t
gh
) - (
t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#54 + #43 + #56
)
+
(
#42
) - (
#24 + #32 + #38
)
6.1 ns= (7.4 + 2.3 + 7.6) + (7.3) - (4.3 + 6.7 + 7.5)
t
co
= Clock (max) + Reg co + Output
=
(
t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(
t
gco
)
+
(
t
orp +
t
ob
)
=
(
#54 + #43 + #56
)
+
(
#43
)
+
(
#48 + #50
)
30.9 ns = (7.4 + 2.3 + 7.6) + (7.3) + (3.4 + 2.9)
1. Calculations are based upon timing specifications for the ispLSI 1048C-50
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