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參數(shù)資料
| 型號(hào)： | 1032 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | 在系統(tǒng)可編程高密度可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 151K |
| 代理商： | 1032 |
Specifications
ispLSI 1032/883
2
Functional Block Diagram
Figure 1. ispLSI 1032/883 Functional Block Diagram
The device also has 64 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional I/O pin with
3-state control. Additionally, all outputs are polarity se-
lectable, active high or active low. The signal levels are
TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. The I/O cells
within the Megablock also share a common Output
Enable (OE) signal. The ispLSI 1032/883 device con-
tains four of these Megablocks.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1032/883 device are selected using
the Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (C0 on the ispLSI
1032/883 device). The logic of this GLB allows the user
to create an internal clock from a combination of internal
signals within the device.
Y
0
Y
1
Y
2
Y
3
I/O 0
I/O 1
I/O 2
I/O 3
IN 5
IN 4
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
SDI/IN 0
MODE/IN 1
I/O
62
I/O
63
I/O
61
I/O
60
I/O
59
I/O
58
I/O
57
I/O
56
I/O
55
I/O
54
I/O
53
I/O
52
I/O
51
I/O
50
I/O
49
I/O
48
IN
7
IN
6
I/O
17
I/O
16
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
SDO/IN 2
SCLK/IN 3
I/O 4
I/O 5
RESET
Global
Routing
Pool
(GRP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Clock
Distribution
Network
D7
D6
D5
D4
D3
D2
D1
D0
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
C7
C6
C5
C4
C3
C2
C1
C0
O
Generic
Logic Blocks
(GLBs)
Megablock
O
Input Bus
Input Bus
I
ispEN
l
0139(1)-32-isp
相關(guān)PDF資料 |
PDF描述 |
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| 10371QC | Shielded Paired Cable; Number of Conductors:8; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyethylene; Number of Pairs:4; Features:Alumunium Foil Polyester/Tinned Copper Braid; Impedance:100ohm RoHS Compliant: Yes |
| 10371QI | Shielded Paired Cable; Number of Conductors:8; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyethylene; Number of Pairs:4; Features:Alumunium Foil Polyester/Tinned Copper Braid; Impedance:100ohm RoHS Compliant: Yes |
| 100371 | Low Power Triple 4-Input Multiplexer with Enable(低功耗、帶使能端的四組4輸入多路轉(zhuǎn)換器) |
| 10371QCX | 4-Input Digital Multiplexer |
| 10371QIX | 4-Input Digital Multiplexer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| 10-32 | 制造商:Calrad Electronics 功能描述: |
| 10-32 AJ 6 | 功能描述:螺絲和緊固件 SEELNUTS 10-32 THREAD RoHS:否 制造商:Unspecified 產(chǎn)品: 類(lèi)型:Washer 螺紋大小: 長(zhǎng)度: 材料:Steel 電鍍:Nickel 螺絲頭: 螺絲類(lèi)型: |
| 1032/SF-8 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:KEGELKNOPF SELBSFIXIEREND M8 10ST |
| 10320 | 功能描述:模擬面板表 1359 0-150 ACV 4. RoHS:否 制造商:Simpson Electric Company 設(shè)備類(lèi)型:AC Current Meter 范圍:0 - 5 大小:4.88 in |
| 10-320 | 制造商:GC Electronics 功能描述:Radio-Tv Cement Solvent |
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