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參數(shù)資料
| 型號(hào)： | 1024 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | Shielded Paired Cable; Number of Conductors:8; Conductor Size AWG:28; No. Strands x Strand Size:7 x 36; Jacket Material:Polyethylene; Number of Pairs:4; Features:Alumunium Foil Polyester/Tinned Copper Braid; Impedance:120ohm RoHS Compliant: Yes |
| 中文描述： | 在系統(tǒng)可編程高密度可編程邏輯器件 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 147K |
| 代理商： | 1024 |
Specifications
ispLSI 1024/883
10
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
NAME
Table 2 - 0002C-24 mil
JLCC
PIN NUMBERS
DESCRIPTION
22,
26,
30,
37,
41,
45,
56,
60,
64,
3,
7,
11,
23,
27,
31,
38,
42,
46,
57,
61,
65,
4,
8,
12,
24,
28,
32,
39,
43,
47,
58,
62,
66,
5,
9,
13,
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
25,
29,
33,
40,
44,
48,
59,
63,
67,
6,
10,
14
54
Y1
16
Y0
55
MODE/IN 31
Input - This pin performs two functions. When ispEN is logic low, it
functions as pin to control the operation of the isp state machine. It is a
dedicated input pin when ispEN is logic high.
Output/Input - This pin performs two functions. When ispEN is logic low,
it functions as an output pin to read serial shift register data. It is a
dedicated input pin when ispEN is logic high.
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. It is a dedicated
input pin when ispEN is logic high.
No Connect
Ground (GND)
GND
V
VCC
CC
IN 4 - IN 5
2,
15
Input - These pins are dedicated input pins to the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO
and SCLK options become active.
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 is also used as one of the two control pins for the isp state
machine. It is a dedicated input pin when ispEN is logic high.
19
ispEN
21
SDI/IN 01
34
SDO/IN 11
49
SCLK/IN 21
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
20
RESET
51
Y2
50
Y3
1,
18,
35,
52
17,
36,
53,
68
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, Vcc or GND.
NC2
—
Pin Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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