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參數(shù)資料
| 型號： | 101-0518 |
| 廠商： | Rabbit Semiconductor |
| 文件頁數(shù)： | 6/110頁 |
| 文件大?。?/td> | 0K |
| 描述： | MODULE RABBITCORE RCM3110 |
| 標(biāo)準包裝： | 50 |
| 系列： | RabbitCore® |
| 模塊/板類型： | MPU 核心模塊 |
| 適用于相關(guān)產(chǎn)品： | RCM3110 |
| 其它名稱： | 316-1022 |
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User’s Manual
97
The Quadrature Decoder generates an interrupt when the counter increments from 0x00 to
0x01 or when the counter decrements from 0x00 to 0xFF. Note that the status bits in the
QDCSR are set coincident with the interrupt, and the interrupt (and status bits) are cleared
by reading the QDCSR.
Table E-5. Quadrature Decoder Registers
Register Name
Mnemonic
Address
Quad Decode Control/Status
Register
QDCSR
10010000 (0x90)
Bit
Value
Description
7
(rd-only)
0
Quadrature Decoder 2 did not increment from 0xFF.
1
Quadrature Decoder 2 incremented from 0xFF to
0x00. This bit is cleared by a read of this register.
6
(rd-only)
0
Quadrature Decoder 2 did not decrement from 0x00.
1
Quadrature Decoder 2 decremented from 0x00 to
0xFF. This bit is cleared by a read of this register
5
0
This bit always reads as zero.
4
(wr-only)
0
No effect on the Quadrature Decoder 2.
1
Reset Quadrature Decoder 2 to 0x00, without
causing an interrupt.
3
(rd-only)
0
Quadrature Decoder 1 did not increment from 0xFF.
1
Quadrature Decoder 1 incremented from 0xFF to
0x00. This bit is cleared by a read of this register.
2
(rd-only)
0
Quadrature Decoder 1 did not decrement from 0x00.
1
Quadrature Decoder 1 decremented from 0x00 to
0xFF. This bit is cleared by a read of this register.
1
0
This bit always reads as zero.
Bit
Value
Description
0
(wr-only)
0
No effect on the Quadrature Decoder 1.
1
Reset Quadrature Decoder 1 to 0x00, without
causing an interrupt.
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| 10-105-2-05 | 制造商:Concord Electronics Inc 功能描述: |
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