參數(shù)資料
型號(hào)： 100LVEL16M
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類(lèi)： 通用總線功能
英文描述： 3.3V ECL Differential Receiver
中文描述： LINE RECEIVER, PDSO8
封裝： 0.150 INCH, MS-012, SOIC-8
文件頁(yè)數(shù)： 3/6頁(yè)
文件大?。?/td> 141K
代理商： 100LVEL16M
3
www.fairchildsemi.com
1
LVNECL DC Electrical Characteristics
V
CC
=
0.0V; V
EE
=
3.3V (Note 6)
Note 6:
Input and output parameters vary 1 to 1 with V
CC
. V
EE
can vary
±
0.3V.
Note 7:
Outputs are terminated through a 50
Resistor to V
CC
2.0V.
Note 8:
V
IHCMR
minimum varies 1 to 1 with V
EE
. V
IHCMR
maximum varies 1-to-1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the
differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PPMIN
and
1V.
Note 9:
Absolute value of the input HIGH and LOW current should not exceed the absolute value of the stated Min or Max specification.
Note:
Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than
500LFPM maintained.
100LVEL16 AC Electrical Characteristics
V
CC
=
3.3V; V
EE
=
0.0V or V
CC
=
0.0V; V
EE
=
3.3V
(Note 10) (Note 11)
Note 10:
V
EE
can vary
±
0.3V.
Note 11:
Measured using a 750 mV input swing centered at V
CC
- 1.32V; 50% duty cycle clock source; t
r
=
t
f
=
250 ps (20% - 80%) at f
IN
=
1 MHz. All loading
with 50
to V
CC
2.0V.
Note 12:
Duty cycle skew is the difference between a t
PLH
and t
PHL
propagation delay through a device under identical conditions.
Symbol
Parameter
40
°
C
Typ
17
1005
1695
25
°
C
Typ
17
955
1705
85
°
C
Typ
18
955
1705
Units
Min
Max
23
880
1555
880
1475
1.26
Min
Max
23
880
1620
880
1475
1.26
Min
Max
24
880
1620
880
-1475
1.26
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Power Supply Current
Output HIGH Voltage (Note 7)
mA
mV
1085
1830
1165
1810
1.38
1025
1810
1165
1810
1.38
1025
1810
1165
1810
1.38
Output LOW Voltage (Note 7)
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
mV
mV
mV
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
V
V
PP
<
500mV
V
PP
≥
500mV
2.5
1.8
0.4
0.4
150
2.5
1.9
0.4
0.4
150
2.5
1.9
0.4
0.4
150
V
I
IH
I
IL
Input HIGH Current
μ
A
Input LOW Current
D
D
0.5
600
0.5
600
0.5
600
μ
A
Symbol
Parameter
40
°
C
Typ
TBD
275
275
25
°
C
Typ
TBD
300
300
85
°
C
Typ
TBD
315
315
Units
Figure
Number
Min
Max
Min
Max
Min
Max
f
MAX
t
PLH
, t
PHL
Maximum Toggle Frequency
Propagation Delay to Output (Diff)
GHz
150
100
400
450
225
175
375
425
240
190
390
440
ps
Figures
1, 3
(SE)
t
SKEW
t
JITTER
V
PP
t
r
, t
f
Duty Cycle Skew (Note 12)
Cycle-to-Cycle Jitter
Input Swing
5
30
5
20
5
20
ps
ps
mV
TBD
TBD
TBD
150
1000
150
1000
150
1000
Figure 1
Output Rise Times Q (20% to 80%)
120
220
320
120
220
320
120
220
320
ps
Figure 2
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