參數(shù)資料
型號: 100355D
廠商: National Semiconductor Corporation
英文描述: Low Power Quad Multiplexer/Latch
中文描述: 低功耗四復用器/鎖存
文件頁數(shù): 1/10頁
文件大小: 148K
代理商: 100355D
100355
Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of which
can accept and store data from two sources. When both En-
able (E
) inputs are LOW, the data that appears at an output
is controlled by the Select (S
) inputs, as shown in the Oper-
ating Mode table. In addition to routing data from either D
or
D
, the Select inputs can force the outputs LOW for the case
where the latch is transparent (both Enables are LOW) and
can steer a HIGH signal from either D
or D
to an output.
The Select inputs can be tied together for applications re-
quiring only that data be steered from either D
or D
. A
positive-going signal on either Enable input latches the out-
puts. A HIGH signal on the Master Reset (MR) input over-
rides all the other inputs and forces the Q outputs LOW. All
inputs have 50 k
pulldown resistors.
Features
n
Greater than 40% power reduction of the 100155
n
2000V ESD protection
n
Pin/function compatible with 100155
n
Voltage compensated operating range = 4.2V to 5.7V
n
Standard Microcircuit Drawing
(SMD) 5962-9165401
Logic Symbol
Pin Names
E
1
, E
2
S
0
, S
1
MR
D
na
–D
nd
Q
a
–Q
d
Q
a
–Q
d
Description
Enable Inputs (Active LOW)
Select Inputs
Master Reset
Data Inputs
Data Outputs
Complementary Data Outputs
Connection Diagrams
DS100294-1
24-Pin DIP
DS100294-2
24-Pin Quad Cerpak
DS100294-3
August 1998
1
1998 National Semiconductor Corporation
DS100294
www.national.com
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