參數(shù)資料
型號(hào): 100331
廠商: National Semiconductor Corporation
英文描述: Low Power Triple D Flip-Flop
中文描述: 低功耗三D觸發(fā)器
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 150K
代理商: 100331
100331
Low Power Triple D Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CP
), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CP
), Direct
Set (SD
) and Direct Clear (CD
) inputs. Data enters a mas-
ter when both CP
and CP
are LOW and transfers to a
slave when CP
or CP
(or both) go HIGH. The Master Set,
Master Reset and individual CD
and SD
inputs override
the Clock inputs. All inputs have 50 k
pull-down resistors.
Features
n
35% power reduction of the 100131
n
2000V ESD protection
n
Pin/function compatible with 100131
n
Voltage compensated operating range = 4.2V to 5.7V
n
Available to industrial grade temperature range
n
Available to Standard Microcircuit Drawing (SMD)
5962-9153601
Logic Symbol
Pin Names
CP
0
–CP
2
CP
C
D
0
–D
2
CD
0
–CD
2
SD
n
MR
MS
Q
0
-Q
2
Q
0
–Q
2
Description
Individual Clock Inputs
Common Clock Input
Data Inputs
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
Data Outputs
Complementary Data Outputs
Connection Diagrams
DS100300-1
24-Pin DIP
DS100300-2
24-Pin Quad Cerpak
DS100300-3
August 1998
1
1998 National Semiconductor Corporation
DS100300
www.national.com
相關(guān)PDF資料
PDF描述
100331D Low Power Triple D Flip-Flop
100331F Low Power Triple D Flip-Flop
100331 Low Power Triple D-Type Flip-Flop
100331PC Low Power Triple D-Type Flip-Flop
100331QI Low Power Triple D-Type Flip-Flop
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