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參數(shù)資料
| 型號： | 08906-004-XTD |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 359K |
| 代理商： | 08906-004-XTD |
AMIS-50050: Spread Spectrum Baseband Controller
Data
Sheet
Wireless Products
Table 3: Pin Descriptions
Pin Name
Type
Functional Description
AGND1
Analog GND
GND1
Ground
VDD1
Vdd
OSC1
Input
Crystal oscillator or external reference input, this input is divided by OSCDIV to generate the reference clock for
the transmit PLL
OSC2
Padosc
Xtal osc output
PLL[3:0]
Output
Off-chip PLL programming; Bit0, Enable1, Bit1; Sclk, Bit2, Enable0, Bit3, Sdata
TXD0
Output
Transmit data “I” output
TXD1
Output
Transmit data “Q” output, or QAM output clock
EPOCH1
Output
Transmit PN generator Epoch signal, (68 pin PLCC package only)
PN1
Output
Transmit PN generator output, can be internally disabled (PMR Bit 4)
GND2
Ground
EXT[3:0]
Output
External control port (lower bits), user defined functions for radio control
VDD2
Vdd
EXT[7:4]
Output
External control port (upper bits), user defined functions for radio control
EXT[9:8]
Output
External control port (upper bits), user defined functions for radio control (68 pin PLCC package only)
INT
Output
Active high – initiates an interrupt to the microprocessor
RESET
Input
Active low – sets all registers to standby states
CS
Input
Active low – selects the chip for reading and writing via the P interface
RD
Input
Active low – initiates a read operation via the P interface
WR
Input
Active low – initiates a write operation via the P interface
GND3
Ground
DATA[7:0]
BIDirection
P interface data bus
ADDR[6:0]
Input
P interface address bus
VDD3
Vdd
GND4
Ground
DUMP
Output
Integrate and dump control logic output
EPOCH2
Output
Receive PN Generator Epoch signal (68 pin PLCC package only)
PN2
Output
Receive PN generator output
RCVRY
BIDirection
Clock recovery input for narrow band mode, track-on (active high) output for spread spectrum mode – indicates
to external circuitry that the PN code is locked and tracking the received PN code
TEST
Input
Pin for manufacturing test only – should be tied to ground for normal operation
RXD1
Analog I/O
Receive data input “Q” or QAM mode output clock to external shift register
RXD0
Analog In
Receive data input “I”
VREFD
Analog In
Reference voltage for integrate and dump comparators and switches
AGND2
Analog GND
VCO2
Analog Input
Receive VCO control voltage output
AVDD2
Analog VDD
DACOUT1
Analog Output
Receive DAC output during TRACK operation – Note: DACOUT0 and DACOUT1 are provided in the event that
separate gain control is necessary for SLIP and TRACK operation
DACOUT0
Analog Output
Receive PLL DAC output during SLIP operation
RBIAS
Analog Input
Current reference for DACs and analog buffers – nominal resistor value of 20k to AGND3
VREF
Analog Input
Reference voltage for ADC and DACs – value is mid-scale between VDD and GND
AGND3
Analog GND
RSSI1
Analog Input
Analog input to the ADC – received signal strength indicator from the RF receiver, range is zero to VREF (full
scale on the internal ADC)
RSSI2
Analog Input
Analog input to the ADC – received signal strength indicator from the RF receiver, range is zero to VREF (full
scale on the internal ADC) This input is not usable in “SLIP” mode.
AVDD3
Analog VDD
AVDD1
Analog VDD
VCO1
Analog I/O
Transmit VCO voltage control output
5
AMI Semiconductor
– Sept. 06
www.amis.com
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