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參數(shù)資料
| 型號： | 0804-5000-19 |
| 廠商： | BEL FUSE INC |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT AC-DC REG PWR SUPPLY MODULE |
| 封裝： | ROHS COMPLIANT, MODULE-40 |
| 文件頁數(shù)： | 2/3頁 |
| 文件大小： | 312K |
| 代理商： | 0804-5000-19 |
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 Tel 201-432-0463 Fax 201-432-9542 www.belfuse.com
2009 Bel Fuse Inc. Specifications subject to change without notice. 08.06.09
POWERLINE MODULES
Turbo SIMPLE PowerPacket Modules
Industrial Temperature Range
Page 1
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 Tel 201-432-0463 Fax 201-432-9542 www.belfuse.com
2009 Bel Fuse Inc. Specifications subject to change without notice. 08.06.09
Page 2
POWERLINE MODULES
Turbo SIMPLE PowerPacket Modules
Industrial Temperature Range
The 0804-5000-19 has been introduced to extend Bel’s range of Powerline modules providing higher speed communications
up to 85 Mbps over the powerline. The Single Inline Module devices incorporate the Intellon Baseband/AFE ICs and required
support circuitry to provide a single component solution for the addition of powerline functionality to a product.
The SIMPLE (Single Inline Module – Power Line Enabled) family architecture is designed so that as new Baseband and
AFE ICs become available the range of modules can be extended. Products incorporating modules can be upgraded to future
SIMPLE modules to provide improved performance, functionality and/ or reduced cost with minimum adaptation of existing
product designs.
The modules are connected to the host system using Intellon’s proprietary SIMPLE PowerBus architecture. SIMPLE
PowerBus provides all the required interface signals between the module and the host system on a single 40-pin
connector. This connector allows the module to be easily installed or removed if a socket is used on the host board, or the
module may be directly soldered onto the host board for reduced cost.
The INT5500CS Chipset
The Bel 0804-5000-19 Turbo Powerline module is based on the Intellon INT5500CS chipset. This chipset is comprised of the
INT5500, an integrated powerline MAC/ PHY transceiver, and its companion INT1200, an analog front end IC.
The INT5500CS chipset provides a highly integrated and optimized solution for networking adapters and embedded products.
It offers the higher bandwidth performance necessary to drive next-generation home entertainment applications, including
standard definition (SD) video distribution, TV over IP (IPTV), digital video recorder (DVR) networking and media center PCs.
Other applications include whole house audio, extension and bridging of higher speed wireless technologies such as 802.11x
and UWB, and higher data-rate broadband sharing based on technologies such as ADSL2 and fiber to the home.
The MAC implements a CSMA/CA scheme with prioritization and automatic repeat request (ARQ) for reliable delivery of
Ethernet packets via packet encapsulation. Built-in Quality of Service (QoS) features provide the necessary bandwidth for
multimedia payloads including voice, data, audio, and video. A four-level prioritized random access method exists with strict
adherence to priority. Segment bursting on the power line minimizes the demands on the receiver resources and maximizes
the throughput of the network, while still providing excellent latency response and jitter performance. The contention-free
access capability extends this concept of segment bursting to allow the transmission of multiple frames over the power line
without relinquishing the control of the medium.
The INT5500CS provides two types of host interface for maximum system flexibility:
An MII PHY (IEEE 802.3u) interface for interconnection to Ethernet controllers
An MII Host / DTE interface (IEEE 802.3u) for direct connection to an Ethernet PHY
The INT5500CS implements Intellon’s patented OFDM technology, which forms the basis for the HomePlug 1.0 specification.
Tailored to reliably deliver up to 85 Mbps over the difficult power line communication environment, the chipset combats deep
attenuation notches, noise sources, and multi-path fading by allocating usable frequencies according to the signal to noise ratio
(SNR). Synchronization is achieved in low SNR channels without the use of pilot carriers. Inclusion of additional modulation
schemes (QAM 256/64/16) increases the chipset’s capability to attain higher throughput performance.
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