參數(shù)資料
型號： 05F6919
英文描述： IC-MONOLITHIC MULTIPLIER
中文描述： 集成電路整裝乘數(shù)
文件頁數(shù)： 5/12頁
文件大?。?/td> 347K
代理商： 05F6919
AD524A
AD524B
AD524C
AD524S
Model
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
GAIN
Gain Equation
(External Resistor Gain
Programming)
Gain Range (Pin Programmable)
1 to 1000
Gain Error
1
G = 1
±0.05
±0.03
±0.02
±0.05 %
G = 10
±0.25
±0.15
±0.1
±0.25 %
G = 100
±0.5
±0.35
±0.25
±0.5
%
G = 1000
±2.0
±1.0
±0.5
±2.0
%
Nonlinearity
G = 1
±0.01
±0.005
±0.003
±0.01 %
G = 10,100
±0.01
±0.005
±0.003
±0.01 %
G = 1000
±0.01
±0.01 %
Gain vs. Temperature
G = 1
5555
ppm/
°C
G = 10
15
10
ppm/
°C
G = 100
35
25
ppm/
°C
G = 1000
100
50
ppm/
°C
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage
250
100
50
100
V
vs. Temperature
2
0.75
0.5
2.0
V/°C
Output Offset Voltage
5
3
2.0
3.0
mV
vs. Temperature
100
50
25
50
V/°C
Offset Referred to the
Input vs. Supply
G = 1
70
75
80
75
dB
G = 10
85
95
100
95
dB
G = 100
95
105
110
105
dB
G = 1000
100
110
115
110
dB
INPUT CURRENT
Input Bias Current
50
25
15
50
nA
vs. Temperature
±100
pA/
°C
Input Offset Current
35
15
10
35
nA
vs. Temperature
±100
pA/
°C
INPUT
Input Impedance
Differential Resistance
10
9
10
9
10
9
10
9
Differential Capacitance
10
pF
Common-Mode Resistance
10
9
10
9
10
9
10
9
Common-Mode Capacitance
10
pF
Input Voltage Range
Max Differ. Input Linear (VDL)
2
±10
V
Max Common-Mode Linear (VCM)
V
Common-Mode Rejection dc to
60 Hz with 1 k
Source Imbalance
G = 1
70
75
80
70
dB
G = 10
90
95
100
90
dB
G = 100
100
105
110
100
dB
G = 1000
110
115
120
110
dB
OUTPUT RATING
VOUT, RL = 2 k
±10
V
DYNAMIC RESPONSE
Small Signal – 3 dB
G = 1
1
MHz
G = 10
400
kHz
G = 100
150
kHz
G = 1000
25
kHz
Slew Rate
5.0
V/
s
Settling Time to 0.01%, 20 V Step
G = 1 to 100
15
s
G = 1000
75
s
NOISE
Voltage Noise, 1 kHz
R.T.I.
7
nV/
√Hz
R.T.O.
90
nV
√Hz
R.T.I., 0.1 Hz to 10 Hz
G = 1
15
V p-p
G = 10
2
V p-p
G = 100, 1000
0.3
V p-p
Current Noise
0.1 Hz to 10 Hz
60
pA p-p
AD524–SPECIFICATIONS
40 , 000
R
G
+ 1
± 20%
40 , 000
R
G
+ 1
± 20%
–2–
REV. B
(@ VS =
15 V, RL = 2 k
and TA = +25 C unless otherwise noted)
40 , 000
R
G
+ 1
± 20%
40 , 000
R
G
+ 1
± 20%
12 V –
G
2
× V
D
12 V –
G
2
× V
D
12 V –
G
2
× V
D
12 V –
G
2
× V
D
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