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參數資料
| 型號： | μPD98401A |
| 廠商： | NEC Corp. |
| 英文描述： | ATM SAR Chip(高性能異步傳輸模式控制器) |
| 中文描述： | 自動柜員機特區(qū)芯片（高性能異步傳輸模式控制器） |
| 文件頁數： | 1/4頁 |
| 文件大?。?/td> | 29K |
| 代理商： | ΜPD98401A |
The μPD98401A is a high-performance Asynchronous Transfer Mode (ATM) controller that implements
ATM protocol layer and adaptation layer (AAL) functions with an advanced architecture optimized for
minimal host CPU and I/O bus utilization. The μPD98401A integrates a 32-bit DMA controller for bus
master operations and an efficient buffer management scheme for reduced buffer memory require-
ment, and also provides CRC-10 generation and verification for AAL-3/4 and OAM cells.
The μPD98401 performs all AAL-5 functions, including segmentation and re-assembly (SAR). The seg-
mented data, based on the various ATM adaptation types, is processed by the μPD98401A into ATM
cells.
μP D 9 8 4 0 1 A S A R A N D A T M L A Y E R C O N T R O L L E R
B L O C K
D I A G R A M
System
Port
DMA
Controller
and
Host
Interface
Receive
PHY
Control
Memory
Control
Memory
Interface
Transmit
PHY
Receive Data FIFO
Sequencer
Transmit Data FIFO
Receive Controller
Transmit Controller
Receive
PHY
Interface
Transmit
PHY
Interface
F E A T U R E S
ATM layer and AAL functions compliant with ITU-TS standard and ATM Forum
specifications
Full AAL-5 support for implementing other ATM adaptation types
Up to 32K active virtual channels for high-end server applications
Traffic shaping using dual leaky bucket scheduling algorithms; traffic handling based on
specified priority level, specified average, and peak traffic rates
Extremely flexible buffer management scheme for efficient utilization of memory space
Integrated FIFOs for receive and transmit cell buffering
Re-assembly timer to terminate buffering of received cells associated with an erroneous frame
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