參數(shù)資料
型號(hào)： μPD9210FGC-7EA
廠商： NEC Corp.
英文描述： USB Host Controller(USB主控制器)
中文描述： USB主機(jī)控制器（的USB主控制器）
文件頁(yè)數(shù)： 62/95頁(yè)
文件大?。?/td> 423K
代理商： ΜPD9210FGC-7EA
CHAPTER 5 REGISTER INFORMATION
62
Table 5-6. I/O Address Register (PC/AT) Information
Field
bit
Read/
Write
Value
(Default)
Comment
I/O space indicator
0
R
1b
Legacy register is mapped to the I/O space.
Reserved
1
R
0b
Reserved
Base address (LSB)
2
R
0b
Legacy register has an 8-byte address space.
Base address (MSB)
31 : 3
R/W
000h
Indicates the high-order 29 bits of the base
address in the Legacy register.
Remark
The I/O Address register is fixed to 0h when legacy support is invalid.
On the other hand, when legacy support is valid, the I/O Address Register (PC-98 Series: offset
address 18h) is fixed at 0h.
Table 5-7. Power Management Control/Status Information
Field
bit
Read/
Write
Value
(Default)
Comment
Power State
1 : 0
R/W
00b
Power State Control bit
00b = D0 (PCI CLK Full mode: Default)
01b = Reserved
10b = D2 (PCI CLK Stop and Device power on)
11b = D3 (PCI CLK Stop and Device power off)
Status Change Standby
2
R
0b
Indicates the device state in relation to control of
Power State transitions
0b = Not Ready
1b = Ready
Bus Master Control
3
R/W
0b
Controls PCI command register’s bit 2 (bus master bit)
0b = Bus master bit is invalid (ordinary bus
master operation)
1b = Bus master bit is valid
Reserved
4
R
0b
Reserved
REQ_Enable
5
R/W
0b
REQ signal output timing control
0b = PCI clock synchronous output: Default
1b = PCI clock asynchronous output
PC_mode
6
R/W
0b
PC-98 Series / PC/AT switch setting control
0b = PC-98 Series mode: Default
1b = PC/AT mode
ID Write Mask
7
R/W
0b
Write protection of Subsystem ID and Subsystem
Vendor ID
0b = Write Mask: Default
1b = Write Enable
Wakeup_Status
8
R/W
0b
“1” is set when a Wakeup request has been
issued. Writing “1” clears the bit, but writing “0”
does not change it.
Reserved
15 : 9
R
0b
Reserved
Wakeup_Enable
16
R/W
0b
Output control of WAKE signal
0b = WAKE signal is invalid: Default
1b = WAKE signal is valid
Reserved
31 : 17
R
0b
Reserved
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