26
LIST OF FIGURES (2/8)
Figure No.
Title
Page
6-18.
6-19.
6-20.
6-21.
6-22.
P130 and P131 Block Diagram .....................................................................................................
Port Mode Register Format ...........................................................................................................
Pull-Up Resistor Option Register Format ......................................................................................
Memory Expansion Mode Register Format...................................................................................
Key Return Mode Register Format................................................................................................
149
152
153
154
155
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
Block Diagram of Clock Generator................................................................................................
Subsystem Clock Feedback Resistor............................................................................................
Processor Clock Control Register Format .....................................................................................
Oscillation Mode Selection Register Format .................................................................................
Main System Clock when Writing to OSMS ..................................................................................
External Circuit of Main System Clock Oscillator ..........................................................................
External Circuit of Subsystem Clock Oscillator .............................................................................
Examples of Incorrect Oscillator Connection ................................................................................
Main System Clock Stop Function ................................................................................................
System Clock and CPU Clock Switching ......................................................................................
160
161
162
164
164
165
166
166
170
173
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
16-Bit Timer/Event Counter Block Diagram...................................................................................
16-Bit Timer/Event Counter Output Control Circuit Block Diagram ...............................................
Timer Clock Selection Register 0 Format......................................................................................
16-Bit Timer Mode Control Register Format..................................................................................
Capture/Compare Control Register 0 Format ...............................................................................
16-Bit Timer Output Control Register Format ................................................................................
Port Mode Register 3 Format ........................................................................................................
External Interrupt Mode Register 0 Format ...................................................................................
Sampling Clock Select Register Format........................................................................................
Control Register Settings for Interval Timer Operation..................................................................
Interval Timer Configuration Diagram............................................................................................
Interval Timer Operation Timings ..................................................................................................
Control Register Settings for PWM Output Operation...................................................................
Example of D/A Converter Configuration with PWM Output .........................................................
TV Tuner Application Circuit Example ...........................................................................................
Control Register Settings for PPG Output Operation ....................................................................
Control Register Settings for Pulse Width Measurement with Free-Running Counter and
One Capture Register ...................................................................................................................
Configuration Diagram for Pulse Width Measurement by Free-Running Counter ........................
Timing of Pulse Width Measurement Operation by Free-Running Counter and
One Capture Register (with Both Edges Specified) ......................................................................
Control Register Settings for Two Pulse Width Measurements with Free-Running Counter ........
Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified) ..........................................................................................................
Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers..................................................................................................................
179
180
183
185
186
187
188
189
190
191
192
192
194
195
195
196
197
198
8-18.
8-19.
198
199
8-20.
8-21.
200
8-22.
201