
17
LIST OF FIGURES (1/5)
Figure No.
Title
Page
2-1.
Pin Input/Output Circuits........................................................................................................................... 42
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
Memory Map (
μ
PD789166Y and
μ
PD789176Y) ....................................................................................... 43
Memory Map (
μ
PD789167Y and
μ
PD789177Y) ....................................................................................... 44
Memory Map (
μ
PD78F9177Y) .................................................................................................................. 45
Data Memory Addressing Modes (
μ
PD789166Y and
μ
PD789176Y)........................................................ 47
Data Memory Addressing Modes (
μ
PD789167Y and
μ
PD789177Y)........................................................ 48
Data Memory Addressing Modes (
μ
PD78F9177Y)................................................................................... 49
Program Counter Configuration ................................................................................................................ 50
Program Status Word Configuration ......................................................................................................... 50
Stack Pointer Configuration ...................................................................................................................... 52
Data to be Saved to Stack Memory .......................................................................................................... 52
Data to be Restored from Stack Memory.................................................................................................. 52
General-Purpose Register Configuration.................................................................................................. 53
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
4-15.
4-16.
4-17.
Port Types................................................................................................................................................. 67
Block Diagram of P00 to P05.................................................................................................................... 69
Block Diagram of P10 and P11................................................................................................................. 70
Block Diagram of P20 ............................................................................................................................... 71
Block Diagram of P21 ............................................................................................................................... 72
Block Diagram of P22 and P25................................................................................................................. 73
Block Diagram of P23 and P24................................................................................................................. 74
Block Diagram of P26 ............................................................................................................................... 75
Block Diagram of P30 ............................................................................................................................... 76
Block Diagram of P31 and P32................................................................................................................. 77
Block Diagram of P33 ............................................................................................................................... 78
Block Diagram of P50 to P53.................................................................................................................... 79
Block Diagram of P60 to P67.................................................................................................................... 80
Format of Port Mode Register................................................................................................................... 83
Format of Pull-Up Resistor Option Register 0........................................................................................... 83
Format of Pull-Up Resistor Option Register B2......................................................................................... 84
Format of Pull-Up Resistor Option Register B3......................................................................................... 84
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
Block Diagram of Clock Generation Circuit............................................................................................... 88
Format of Processor Clock Control Register............................................................................................. 89
Format of Suboscillation Mode Register ................................................................................................... 90
Format of Subclock Control Register ........................................................................................................ 91
External Circuit of Main System Clock Oscillator...................................................................................... 92
External Circuit of Subsystem Clock Oscillator......................................................................................... 93