– vii –
LIST OF FIGURES (1/6)
Figure No.
Title
Page
2-1.
Pin Input/Output Circuit List..................................................................................................
23
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
Memory Map (
μ
PD78042F) ..................................................................................................
Memory Map (
μ
PD78043F) ..................................................................................................
Memory Map (
μ
PD78044F) ..................................................................................................
Memory Map (
μ
PD78045F) ..................................................................................................
Memory Map (
μ
PD78P048A) ...............................................................................................
Data Memory Addressing (
μ
PD78042F) ..............................................................................
Data Memory Addressing (
μ
PD78043F) ..............................................................................
Data Memory Addressing (
μ
PD78044F) ..............................................................................
Data Memory Addressing (
μ
PD78045F) ..............................................................................
Data Memory Addressing (
μ
PD78P048A) ...........................................................................
Program Counter Configuration ...........................................................................................
Program Status Word Configuration ....................................................................................
Stack Pointer Configuration..................................................................................................
Data to be Saved to Stack Memory......................................................................................
Data to be Reset from Stack Memory ..................................................................................
General Register Configuration ............................................................................................
27
28
29
30
31
34
35
36
37
38
39
39
40
41
41
42
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
4-15.
Port Types.............................................................................................................................
P00 and P04 Block Diagram ................................................................................................
P01 to P03 Block Diagram ...................................................................................................
P10 to P17 Block Diagram ...................................................................................................
P20, P21, P23 to P26 Block Diagram ..................................................................................
P22 and P27 Block Diagram ................................................................................................
P30 to P37 Block Diagram ...................................................................................................
P70 to P74 Block Diagram ...................................................................................................
P80 and P81 Block Diagram ................................................................................................
P90 to P97 Block Diagram ...................................................................................................
P100 to P107 Block Diagram ...............................................................................................
P110 to P117 Block Diagram ...............................................................................................
P120 to P127 Block Diagram ...............................................................................................
Port Mode Register Format ..................................................................................................
Pull-Up Resistor Option Register Format .............................................................................
61
65
65
66
67
68
69
70
71
72
73
74
75
77
78
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
Clock Generator Block Diagram ...........................................................................................
Feedback Resistor of Subsystem Clock ..............................................................................
Processor Clock Control Register Format............................................................................
Display Mode Register 0 Format ..........................................................................................
Display Mode Register 1 Format ..........................................................................................
External Circuit of Main System Clock Oscillator.................................................................
External Circuit of Subsystem Clock Oscillator....................................................................
Examples of Oscillator with Bad Connection .......................................................................
82
83
84
86
88
89
89
90