81
CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER
Figure 5-2. Format of 16-Bit Timer Mode Control Register
(
μ
PD78014, 78014Y, 78018F, 78018FY, 78014H subseries)
OVF0
Detects overflow of 16-bit timer register
0
Overflow does not occur
1
Overflow occurs
TMC03 TMC02 TMC01
Selects operation mode
and clear mode
Selects output timing of TO0
Occurrence of
interrupt request
Cautions 1. Before setting the clear mode or changing the output timing of TO0, stop the timer operation
(by clearing TMC01 through TMC03 to 0, 0, 0).
2. Set the valid edge of the TI0/INTP0 pin by the external interrupt mode register (INTM0). The
frequency of the sampling clock is selected by the sampling clock select register (SCS).
3. When using the PWM mode, set data to CR00 after setting the PWM mode.
4. When a mode in which the timer is cleared and started on coincidence between TM0 and CR00,
the OVF0 flag is set to 1 when the set value of CR00 is FFFFH and the value of TM0 changes
from FFFFH to 0000H.
Remarks 1.
TO0
: output pin of 16-bit timer/event counter
: input pin of 16-bit timer/event counter
: 16-bit timer register
4.
CR00 : compare register 00
2.
TI0
3.
TM0
Stops operation (clears TM0
to 0)
PWM mode (free running)
Free running mode
Clears and starts at valid edge
of TI0
Clears and start at coinci-
dence between TM0 and
CR00
Not affected
PWM pulse output
Coincidence between TM0
and CR00
Coincidence between TM0
and CR00, or valid edge of
TI0
Coincidence between TM0
and CR00
Coincidence between TM0
and CR00 or valid edge of
TI0
Coincidence between TM0
and CR00
Coincidence between TM0
and CR00 or valid edge of
TI0
Does not occur
Occurs if TM0 and CR00
coincide
7
6
5
4
3
2
Symbol
1
0
FF48H
OVF0
TMC0
TMC01
TMC03 TMC02
0
0
0
0
Address
At reset
R/W
00H
R/W
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1