參數(shù)資料
型號: μPD78012F
廠商: NEC Corp.
元件分類: 8位微控制器
英文描述: 8 Bit Single Chip Microcontrollers
中文描述: 8位單片機微控制器
文件頁數(shù): 59/74頁
文件大小: 567K
代理商: ΜPD78012F
59
μ
PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F
Data Retention Timing (STOP Mode Release by RESET)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Resolution
8
8
8
bit
Overall error
Note
2.7 V
AV
REF
AV
DD
0.6
%
1.8 V
AV
REF
<
2.7 V
1.4
%
Conversion time
t
CONV
2.0 V
AV
DD
5.5 V
19.1
200
μ
s
1.8 V
AV
DD
<
2.0 V
38.2
200
μ
s
Sampling time
t
SAMP
24/f
X
μ
s
Analog input voltage
V
IAN
AV
SS
AV
REF
V
Reference voltage
AV
REF
1.8
AV
DD
V
AV
REF
resistance
R
AIREF
4
14
k
A/D converter characteristics
(T
A
= –40 to +85
°
C, AV
DD
= V
DD
= 1.8 to 5.5 V, AV
SS
= V
SS
= 0 V)
Note
Overall error excluding quantization error (
±
1/2 LSB). It is indicated as a ratio to the full-scale value.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(T
A
= –40 to +85
°
C)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Data retention supply
V
DDDR
1.8
5.5
V
voltage
Data retention supply
I
DDDR
V
DDDR
= 1.8 V
0.1
10
μ
A
current
Subsystem clock stop and feed-
back resister disconnected
Release signal set time
t
SREL
0
μ
s
Oscillation stabilization
t
WAIT
Release by RESET
2
18
/f
X
ms
wait time
Release by interrupt request
Note
ms
Note
In combination with bit 0 to bit 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS), selection
of 2
13
/f
X
and 2
15
/f
X
to 2
18
/f
X
is possible.
V
DD
STOP Instruction Execution
RESET
V
DDDR
Internal Reset Operation
HALT Mode
Operating Mode
t
WAIT
t
SREL
Data Retension Mode
STOP Mode
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