20
3-1.
Pin Input/Output Circuit List................................................................................................
64
4-1.
Pin Input/Output Circuit List................................................................................................
80
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
Memory Map (
μ
PD780053, 780053Y)................................................................................
Memory Map (
μ
PD780054, 780054Y)................................................................................
Memory Map (
μ
PD780055, 780055Y)................................................................................
Memory Map (
μ
PD780056, 780056Y)................................................................................
Memory Map (
μ
PD780058, 780058Y)................................................................................
Memory Map (
μ
PD78F0058, 78F0058Y) ...........................................................................
Data Memory Addressing (
μ
PD780053, 780053Y) ............................................................
Data Memory Addressing (
μ
PD780054, 780054Y) ............................................................
Data Memory Addressing (
μ
PD780055, 780055Y) ............................................................
Data Memory Addressing (
μ
PD780056, 780056Y) ............................................................
Data Memory Addressing (
μ
PD780058, 780058Y) ............................................................
Data Memory Addressing (
μ
PD78F0058, 78F0058Y) ........................................................
Program Counter Format ...................................................................................................
Program Status Word Format.............................................................................................
Stack Pointer Format..........................................................................................................
Data to Be Saved to Stack Memory ...................................................................................
Data to Be Reset from Stack Memory ................................................................................
General Register Configuration ..........................................................................................
83
84
85
86
87
88
92
93
94
95
96
97
98
98
100
100
100
101
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
6-14.
6-15.
6-16.
6-17.
6-18.
6-19.
6-20.
6-21.
Port Types ..........................................................................................................................
P00 and P07 Block Diagram ..............................................................................................
P01 to P05 Block Diagram .................................................................................................
P10 to P17 Block Diagram .................................................................................................
P20, P21, and P23 to P26 Block Diagram .........................................................................
P22 and P27 Block Diagram ..............................................................................................
P20, P21, and P23 to P26 Block Diagram .........................................................................
P22 and P27 Block Diagram ..............................................................................................
P30 to P37 Block Diagram .................................................................................................
P40 to P47 Block Diagram .................................................................................................
Block Diagram of Falling Edge Detection Circuit................................................................
P50 to P57 Block Diagram .................................................................................................
P60 to P63 Block Diagram .................................................................................................
P64 to P67 Block Diagram .................................................................................................
P70 Block Diagram.............................................................................................................
P71 and P72 Block Diagram ..............................................................................................
P120 to P127 Block Diagram .............................................................................................
P130 and P131 Block Diagram ..........................................................................................
Port Mode Register Format ................................................................................................
Pull-up Resistor Option Register Format............................................................................
Memory Expansion Mode Register Format ........................................................................
119
125
125
126
127
128
129
130
131
132
132
133
135
135
136
137
138
139
142
143
144
LIST OF FIGURES (1/8)
Figure No.
Title
Page