25
17-29.
Logic Circuit of SCL Signal .................................................................................................
378
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
Serial Interface Channel 1 Block Diagram .........................................................................
Timer Clock Select Register 3 Format................................................................................
Serial Operation Mode Register 1 Format..........................................................................
Automatic Data Transmit/Receive Control Register Format...............................................
Automatic Data Transmit/Receive Interval Specify Register Format..................................
3-wire Serial I/O Mode Timings ..........................................................................................
Circuit of Switching in Transfer Bit Order ...........................................................................
Basic Transmission/Reception Mode Operation Timings ...................................................
Basic Transmission/Reception Mode Flowchart.................................................................
Internal Buffer RAM Operation in 6-byte Transmission/Reception
(in Basic Transmit/Receive Mode)......................................................................................
Basic Transmission Mode Operation Timings ....................................................................
Basic Transmission Mode Flowchart ..................................................................................
Internal Buffer RAM Operation in 6-byte Transmission (in Basic Transmit Mode) .............
Repeat Transmission Mode Operation Timing ...................................................................
Repeat Transmission Mode Flowchart ...............................................................................
Internal Buffer RAM Operation in 6-byte Transmission (in Repeat Transmit Mode)...........
Automatic Transmission/Reception Suspension and Restart.............................................
System Configuration when Busy Control Option Is Used .................................................
Operation Timing when Busy Control Option Is Used (when BUSY0 = 0) .........................
Busy Signal and Wait Release (when BUSY0 = 0) ............................................................
Operation Timing when Busy & Strobe Control Options Are Used (when BUSY0 = 0)......
Operation Timing of Bit Shift Detection Function by Busy Signal (when BUSY0 = 1) ........
Automatic Data Transmit/Receive Interval Time ................................................................
Operation Timing with Automatic Data Transmit/Receive Function Performed by
Internal Clock......................................................................................................................
381
384
385
386
387
393
394
403
404
405
407
408
409
411
412
413
415
416
417
418
419
420
421
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
18-24.
422
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
Serial Interface Channel 2 Block Diagram .........................................................................
Baud Rate Generator Block Diagram .................................................................................
Serial Operating Mode Register 2 Format..........................................................................
Asynchronous Serial Interface Mode Register Format.......................................................
Asynchronous Serial Interface Status Register Format .....................................................
Baud Rate Generator Control Register Format ..................................................................
Serial Interface Pin Select Register Format .......................................................................
Asynchronous Serial Interface Transmit/Receive Data Format..........................................
Asynchronous Serial Interface Transmission Completion Interrupt Request
Generation Timing ..............................................................................................................
Asynchronous Serial Interface Reception Completion Interrupt Request
Generation Timing ..............................................................................................................
Receive Error Timing ..........................................................................................................
Status of Receive Buffer Register (RXB) and Generation of
Interrupt Request (INTSR) when Reception Is Stopped ....................................................
427
428
430
431
434
435
439
450
452
19-10.
453
454
19-11.
19-12.
455
LIST OF FIGURES (6/8)
Figure No.
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