27
23-3.
23-4.
23-5.
HALT Mode Release by RESET Input................................................................................
STOP Mode Release by Interrupt Request Generation .....................................................
STOP Mode Release by RESET Input ...............................................................................
517
519
520
24-1.
24-2.
24-3.
24-4.
Reset Function Block Diagram ...........................................................................................
Reset Timing by RESET Input............................................................................................
Reset Timing due to Watchdog Timer Overflow .................................................................
Reset Timing by RESET Input in STOP Mode ...................................................................
521
522
522
522
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
ROM Correction Block Diagram .........................................................................................
Correction Address Registers 0 and 1 Format ...................................................................
Correction Control Register Format ...................................................................................
Storing Example to EEPROM (When One Place Is Corrected) .........................................
Initialization Routine ...........................................................................................................
ROM Correction Operation.................................................................................................
ROM Correction Usage Example .......................................................................................
Program Transition Diagram (When One Place Is Corrected) ...........................................
Program Transition Diagram (When Two Places Are Corrected) .......................................
525
526
527
528
529
530
531
532
533
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
Memory Size Switching Register Format ...........................................................................
Internal Expansion RAM Size Switching Register Format .................................................
Communication Mode Selecting Format ............................................................................
Connection of Flashpro II in 3-wire Serial I/O Mode...........................................................
Connection of Flashpro II in UART Mode...........................................................................
Connection of Flashpro II in Pseudo 3-wire Serial I/O Mode .............................................
536
537
539
540
540
541
B-1.
B-2.
B-3.
B-4.
Development Tool Configuration ........................................................................................
EV-9200GC-80 Drawing (For Reference Only) ..................................................................
EV-9200GC-80 Footprint (For Reference Only) .................................................................
TGK-080SDW Drawing (For Reference Only)....................................................................
562
571
572
573
LIST OF FIGURES (8/8)
Figure No.
Title
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