7
Major Revisions in This Edition
Page
Description
P.87
Addition of
Caution
regarding setting values for memory size switching register to
5.1 Memory Spaces
P.161, 162
Change and addition of
Caution
to
8.3 16-bit Timer/Event Counter Configuration (2) Capture/
compare register00(CR00)
,
(3) Capture/compare register01(CR01)
P.163
Change in
Figure 8-2 16-bit Timer Mode Control Register (TMC0) Format
P.164
Addition of
Caution
to
Figure 8-3 Capture/Compare Control Register 0 (CRC0) Format
P.165
Addition of
Note
to
Figure 8-4 16-bit Timer Output Control Register (TOC0) Format
P.166
Change and addition of
Caution
to
Figure 8-5 Prescaler Mode Register 0 (PRM0) Format
P.170
Addition of
Caution
to
Figure 8-10 Control Register Settings for PPG Output Operation
P.172, 174, 176, 177
Revision of following timing charts in
CHAPTER 8 16-BIT TIMER/EVENT COUNTER
Figure 8-13 Timing of Pulse Width Measurement Operation by Free-Running Counter and One
Capture Register (with Both Edges Specified)
Figure 8-16 Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both
Edges Specified)
Figure 8-18 Timing of Pulse Width Measurement Operation by Free-Running Counter and Two
Capture Registers (with Rising Edge Specified)
Figure 8-20 Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge
Specified)
P.178
Addition of
Caution
to
8.5.4 External event counter operation
P.181
8.5.6 One-shot pulse output operation
First sentence about prohibition of one-shot pulse output with external trigger completely changed
P.186, 187
8.6 16-bit Timer/Event Counter Operating Precautions
Revision in
(7) Operation of OVF0 flag
Addition of the following items
(9) Timer operation
(10) Capture operation
(11) Compare operation
(12) Edge detection
P.230
Revision of
Caution
of
13.2 A/D Converter Configuration (2) A/D conversion result register (ADCR0)
P.245
Revision in
13.5 A/D Converter Cautions (10) A/D conversion result register (ADCR0) read
operation
P.248
Revision of
Caution
of
14.2 A/D Converter Configuration (2) A/D conversion result register (ADCR0)
P.260
Revision in
14.5 A/D Converter Cautions (10) A/D conversion result register (ADCR0) read
operation
P.289
Addition of
Note
to
Figure 17-2 Serial Interface (CSIM30) Format
P.297
Revision of
18.3 Registers to Control Serial Interface (1) IIC control register (IICC0)
P.299, 300
Revision of description of STT0 and SPT0 flags in
Figure 18-3 IIC Control Register (IICC0) Format
The mark shows major revised points.