Major Revisions in This Edition
Page
Description
Addition of following products as applicable products:
μ
PD780024, 780024Y, 780034, 780034Y, 78014H, 780924, 780964 subseries,
μ
PD78018F, 78018FY,
780001, 78011F(A), 78012F(A), 78013F(A), 78014F(A), 78015F(A), 78016F(A), 78018F(A), 78P018F(A)
Following register formats and tables are shown for each model.
Tables 3-1 and 3-2 Maximum Time Required to Switch CPU Clock
Figures 3-1 through 3-4 Format of Processor Clock Control Register
Figures 4-1 and 4-2 Format of Timer clock Select Register 2
Figures 4-4 through 4-6 Format of Watchdog Timer Mode Register
Figures 5-2 and 5-3 Format of 16-Bit Timer Mode Control Register
Figures 5-4 and 5-5 Format of 16-Bit Timer Output Control Register
Figures 7-2 and 7-3 Format of Watch Timer Mode Control Register
Figures 9-1 through 9-4 Format of A/D Converter Mode Register
Figures 9-5 and 9-6 Format of A/D Converter Input Select Register
Addition of following register formats:
Figure 4-3 Format of Watchdog Timer Clock Select Register
Figure 5-9 Format of Capture/Compare Control Register 0
Figure 5-10 Format of Prescaler Mode Register 0
Figures 5-11 and 5-14 Format of Port Mode Register 7
Figures 6-2 and 6-3 Format of Timer Clock Select Register 50
Figures 6-4 and 6-5 Format of Timer Clock Select Register 51
Figures 6-6 Format of Timer Clock Select Register 52
Figures 6-8 Format of 8-Bit Timer Mode Control Register 5n
Figures 6-9 Format of 8-Bit Timer Mode Control Register 50
Figures 6-10 Format of 8-Bit Timer Mode Control Register 51
Figures 6-11 Format of 8-Bit Timer Mode Control Register 52
Figure 9-7 Format of Analog Input Channel Specification Register
Addition of Note 2 and Caution 2 to Figure 4-4 Format of Watchdog Timer Mode Register
Addition of Caution to Figure 5-7 Format of External Interrupt Mode Register
Addition of Table 8-2 Registers of Serial Interface
Addition of Caution to Figures 8-6 through 8-8 Format of Serial Operating Mode Register 0, and Note to
Control of Wake-up Function
Addition of Caution to Figure 8-19 Format of Automatic Transmission/Reception Interval Specification
Register
Change of
μ
PD6252 as maintenance part in 8.1 Interface with EEPROM
TM
(
μ
PD6252)
Addition of (5) and (6) Limits when I
2
C bus mode is used to 8.1.2 Communication in I
2
C bus mode
Addition of HSC bit to Figure 9-2 Format of A/D Converter Mode Register
The mark shows major revised points.
p.57, 58
p.59 to p.62
p.70, p71
p73 to p.75
p.81, 82
p.83, 84
p.145, 146
p.264 to p267
p.268, 269
p.72
p.86
p.87
p.87, 133
p.125
p.126
p.127
p.128
p.129
p.130
p.131
p.269
p.73
p.85
p.155
p.161 to p.166
p.182
p.185
p.203
p.265
Throughout