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16
LIST OF FIGURES (2/5)
Fig. No.
Title
Page
7-11
Control Register Settings for Pulse Width Measurement with
Free Running Counter and One Capture Register ................................................................................
Configuration for Pulse Width Measurement with Free Running Counter .............................................
Timing of Pulse Width Measurement with Free Running Counter and
One Capture Register (with both edges specified)................................................................................
Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter.............
CRn1 Capture Operation with Rising Edge Specified............................................................................
Timing of Pulse Width Measurement with Free Running Counter (with both edges specified) .............
Control Register Settings for Pulse Width Measurement
with Free Running Counter and Two Capture Registers .......................................................................
Timing of Pulse Width Measurement with Free Running Counter and
Two Capture Registers (with rising edge specified)...............................................................................
Control Register Settings for Pulse Width Measurement by Restarting ................................................
Timing of Pulse Width Measurement by Restarting (with rising edge specified) ...................................
Control Register Settings in External Event Counter Mode...................................................................
Configuration of External Event Counter ...............................................................................................
Timing of External Event Counter Operation (with rising edge specified)..............................................
Control Register Settings in Square Wave Output Mode.......................................................................
Timing of Square Wave Output Operation.............................................................................................
Control Register Settings for One-Shot Pulse Output with Software Trigger.........................................
Timing of One-Shot Pulse Output Operation with Software Trigger ......................................................
Control Register Settings for One-Shot Pulse Output with External Trigger..........................................
Timing of One-Shot Pulse Output Operation with External Trigger (with rising edge specified)............
Start Timing of 16-Bit Timer Register n..................................................................................................
Timing after Changing Compare Register during Timer Count Operation.............................................
Data Hold Timing of Capture Register...................................................................................................
Operation Timing of OVFn Flag.............................................................................................................
Block Diagram of TM2-TM5...................................................................................................................
Format of TM2, TM3 Timer Clock Selection Register 2 and 3 (TCL2, TCL3)........................................
Format of TM4, TM5 Timer Clock Selection Register 4 and 5 (TCL4, TCL5)........................................
Format of 8-Bit Timer Mode Control Register 2-5 (TMC2-TMC5)..........................................................
Timing of Interval Timer Operation ........................................................................................................
Timing of External Event Counter Operation (when rising edge is set).................................................
Timing of PWM Output...........................................................................................................................
Timing of Operation Based on CRn0 Transitions ..................................................................................
Cascade Connection Mode with 16-Bit Resolution................................................................................
Start Timing of Timer n ..........................................................................................................................
Timing After Compare Register Changes During Timer Counting.........................................................
161
162
7-12
7-13
162
163
164
164
7-14
7-15
7-16
7-17
165
7-18
166
167
167
168
169
169
170
171
172
173
174
175
175
176
176
177
179
181
182
183
185
188
190
191
193
194
194
7-19
7-20
7-21
7-22
7-23
7-24
7-25
7-26
7-27
7-28
7-29
7-30
7-31
7-32
7-33
7-34
7-35
7-36
7-37
7-38
7-39
7-40
7-41
7-42
7-43
7-44
8-1
8-2
8-3
Block Diagram of Watch Timer ..............................................................................................................
Format of Watch Timer Mode Control Register (WTM) .........................................................................
Operation Timing of Watch Timer/Interval Timer...................................................................................
195
197
199
9-1
Block Diagram of Watchdog Timer ........................................................................................................
201