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參數(shù)資料
| 型號： | μPD703001 |
| 廠商： | NEC Corp. |
| 英文描述： | 16/32 Bit Single Chip Microcontrollers(16/32位單片微控制器) |
| 中文描述： | 16/32位單片機微控制器（16/32位單片微控制器） |
| 文件頁數(shù)： | 13/88頁 |
| 文件大?。?/td> | 614K |
| 代理商： | ΜPD703001 |
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13
μ
PD703000, 703001
2. FUNCTION BLOCKS
2.1 Internal Units
2.1.1 CPU
Most instructions, such as address calculation, arithmetic and logic operation, and data transfer, are executed
in one clock cycle under control of 5-stage pipeline.
The CPU also includes dedicated hardware such as a multiplier (16 by 16) and a 32-bit barrel shifter, aiming at
processing complex instructions at high speeds.
In addition, the CPU can access internal ROM (32 KB) and RAM (1 KB) in one clock cycle.
2.1.2 Bus control unit (BCU)
The BCU initiates necessary external bus cycles based on the physical address given by the CPU. When an
instruction fetch is executed from external memory area, if no bus cycle initiation is requested by the CPU, the BCU
creates a prefetch address to prefetch an instruction code. The prefetched instruction code is taken into the internal
instruction queue.
2.1.3 ROM
The ROM has a capacity of 32 KB and is mapped from the address 00000000H. Access to the ROM is enabled/
disabled by setting the MODE0 and MODE1 pins.
The CPU can access any address of the ROM in one clock cycle (to fetch an instruction).
2.1.4 RAM
This RAM has a capacity of 1 KB and is mapped from address FFFFE000H. The CPU can access any address
of the RAM in one clock cycle (to access data).
2.1.5 Port
The
μ
PD703000 is provided with a total of 68 input/output port pins (of which one is an input port pin), or ports
0 through 10. These port pins can be used as the control pins.
2.1.6 Interrupt controller
The interrupt controller controls various interrupt requests (NMI, INTP00-INTP03, and INTP10-INTP13) issued
by peripheral hardware or external devices. Up to eight levels of interrupt priority can be individually specified for
each interrupt request. In addition, multiplexed processing control can be performed.
2.1.7 Clock generator
The clock generator generates a CPU operating clock whose frequency is 5 times as high as (with the internal
PLL) or half (without the internal PLL) the frequency of the resonator connected across the X1 and X2 pins. Instead
of connecting a resonator, a clock signal can be input from off-chip.
2.1.8 Realtime pulse unit (RPU)
The RPU which includes a 16-bit timer/event counter and a 16-bit interval timer, measures pulse intervals
and pulse frequency, and outputs programmable pulses.
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