參數(shù)資料
型號： Z8L182
廠商： ZiLOG, Inc.
英文描述： Smart Peripheral Controller(智能外設(shè)控制器)
中文描述： 智能外設(shè)控制器（智能外設(shè)控制器）
文件頁數(shù)： 1/109頁
文件大?。?/td> 731K
代理商： Z8L182
3-1
Z80182/Z8L182
Z
ILOG
I
NTELLIGENT
P
ERIPHERAL
P R E L I M I N A R Y
Zilog
DS971820600
FEATURES
P
RELIMINARY
P
RODUCT
S
PECIFICATION
I
Z8S180 MPU
- Code Compatible with Zilog Z80
/Z180
CPU
- Extended Instructions
- Operating Frequency: 33 MHz/5V or 20 MHz/3.3V
- Two DMA Channels
- On-Chip Wait State Generators
- Two UART Channels
- Two 16-Bit Timer Counters
- On-Chip Interrupt Controller
- On-Chip Clock Oscillator/Generator
- Clocked Serial I/O Port
- Fully Static
- Low EMI Option
I
Two ESCC
Channels with 32-Bit CRC
I
Three 8-Bit Parallel I/O Ports
I
16550 Compatible MIMIC Interface for
Direct Connection to PC, XT, AT Bus
I
100-Pin Package Styles (QFP, VQFP)
(0.8 Micron CMOS 5120 Technology)
I
Individual WSG for RAMCS and ROMCS
GENERAL DESCRIPTION
The Z80182/Z8L182 is a smart peripheral controller IC for
modem (in particular V. Fast applications), fax, voice
messaging and other communications applications. It
uses the Z80180 microprocessor (Z8S180 MPU core)
linked with two channels of the industry standard Z85230
ESCC (Enhanced Serial Communications Controller), 24
bits of parallel I/O, and a 16550 MIMIC for direct connection
to the IBM PC, XT, AT bus.
The Z80182/Z8L182 allows complete flexibility for both
internal PC and external applications. Also current PC
modem software compatibility can be maintained with the
Z80182/Z8L182 ability to mimic the 16550 UART chip. The
Z80180 acts as an interface between the ESCC
and
16550 MIMIC interface when used in internal applications,
and between the two ESCC channels in the external
applications. This interface allows data compression and
error correction on outgoing and incoming data. In external
applications, three 8-bit parallel ports are available for
driving LEDs or other devices. Figure 1 shows the Z80182/
Z8L182 block diagram, while the pin assignments for the
QFP and the VQFP packages are shown in Figures 2 and
3, respectively. All references in this document to the
Z80182, or Z182 refer to both the Z80182 and Z8L182.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
V
GND
V
DD
V
SS
Z80182/Z8L182
Z
ILOG
I
NTELLIGENT
P
ERIPHERAL
C
ONTROLLER
(ZIP
)
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