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參數(shù)資料
| 型號： | YSS906N |
| 英文描述： | Stratix II GX FPGA 60K FPGA-1152 |
| 中文描述： | 消費性IC |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 代理商： | YSS906N |
YSS902
9
(Registermap continued)
address
Name
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0x26
Bitstream Register 14
langcod2
0x27
Bitstream Register 15
compr
0x28
Bitstream Register 16
compr2
0x29
Bitstream Register 17
dynrng
0x2A
Bitstream Register 18
dynrng2
0x2B
0x2C
0x2D
(not used)
(write disable, all “0” out when read)
0x2E
Data Stream Register
STREAM7 STREAM6 STREAM5 STREAM4 STREAM3 STREAM2 STREAM1 STREAM0
0x2F
Status Register
0
2/0MODE
SURENC KARAOKE
MUTE
CRC
NONPCM
Address 0x06 to 0x08 and 0x37 to 0x7F are assigned for TEST. Never access to these registers.
Please refer to Application manual for details of Control register.
SERIAL DATA INTERFACE
Data timing of the serial data interface is as follows.
Please refer to Application manual for details of SDIA, SDOA, SDIB, and SDOB registers.
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