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參數(shù)資料
| 型號： | XCS10-3PC84C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 22/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 5V C-TEMP 84-PLCC |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 系列： | Spartan® |
| LAB/CLB數(shù)： | 196 |
| 邏輯元件/單元數(shù)： | 466 |
| RAM 位總計： | 6272 |
| 輸入/輸出數(shù)： | 61 |
| 門數(shù)： | 10000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
29
Product Specification
R
Product Obsolete/Under Obsolescence
Express Mode (Spartan-XL Family Only)
Express mode is similar to Slave Serial mode, except that
data is processed one byte per CCLK cycle instead of one
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the con-
figuration data shift registers (Figure 27). A CCLK fre-
quency of 1 MHz is equivalent to a 8 MHz serial rate,
because eight bits of configuration data are loaded per
CCLK cycle. Express mode does not support CRC error
checking, but does support constant-field error checking. A
length count is not used in Express mode.
Express mode must be specified as an option to the devel-
opment system. The Express mode bitstream is not com-
patible with the other configuration modes (see Table 16,
page 32.) Express mode is selected by a <0X> on the Mode
pins (M1, M0).
The first byte of parallel configuration data must be available
at the D inputs of the FPGA a short setup time before the
second rising CCLK edge. Subsequent data bytes are
clocked in on each consecutive rising CCLK edge
(Figure 28).
Pseudo Daisy Chain
Multiple devices with different configurations can be config-
ured in a pseudo daisy chain provided that all of the devices
are in Express mode. Concatenated bitstreams are used to
configure the chain of Express mode devices so that each
device receives a separate header. CCLK pins are tied
together and D0-D7 pins are tied together for all devices
along the chain. A status signal is passed from DOUT to
CS1 of successive devices along the chain. Frame data is
accepted only when CS1 is High and the device’s configura-
tion memory is not already full. The lead device in the chain
has its CS1 input tied High (or floating, since there is an
internal pull-up). The status pin DOUT is pulled Low after
the header is received, and remains Low until the device’s
configuration memory is full. DOUT is then pulled High to
signal the next device in the chain to accept the next header
and configuration data on the D0-D7 bus.
The DONE pins of all devices in the chain should be tied
together, with one or more active internal pull-ups. If a large
number of devices are included in the chain, deactivate
some of the internal pull-ups, since the Low-driving DONE
pin of the last device in the chain must sink the current from
all pull-ups in the chain. The DONE pull-up is activated by
default. It can be deactivated using a development system
option.
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All Spartan-XL devices in Express mode are synchronized
Figure 26: Slave Serial Mode Programming Switching Characteristics
TCCH
Bit n
Bit n + 1
Bit n
Bit n – 1
TCCO
TCCL
TCCD
TDCC
DIN
CCLK
DOUT
(Output)
DS060_26_080400
Symbol
Description
Min
Max
Units
TDCC
CCLK
DIN setup
20
-
ns
TCCD
DIN hold
0
-
ns
TCCO
DIN to DOUT
-
30
ns
TCCH
High time
40
-
ns
TCCL
Low time
40
-
ns
FCC
Frequency
-
12.5
MHz
Notes:
1.
Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are
High.
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