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參數(shù)資料
| 型號： | W7NCF02GH10CSBDM1G |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | FLASH 3.3V PROM MODULE, XMA50 |
| 封裝： | CARD-50 |
| 文件頁數(shù)： | 13/13頁 |
| 文件大?。?/td> | 180K |
| 代理商： | W7NCF02GH10CSBDM1G |
March 2007
Rev. 2
W7NCF-H-M1 Series
9
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
Signal Name
Dir.
Pin
Description
-IOWR
(PC Card Memory Mode)
I35
This signal is not used in this mode.
-IOWR
(PC Card I/O Mode)
The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the
CompactFlash Storage Card or CF+ Card controller registers when the CompactFlash
Storage Card or CF+ Card is congured to use the I/O interface.
The clocking shall occur on the negative to positive edge of the signal (trailing edge).
-IOWR
(True IDE Mode)
In True IDE Mode, this signal has the same function as in PC Card I/O Mode.
-OE
(PC Card Memory Mode)
I9
This is an Output Enable strobe generated by the host interface. It is used to read data from
the CompactFlash Storage Card or CF+ Card in Memory Mode and to read the CIS and
conguration registers.
-OE
(PC Card I/O Mode)
In PC Card I/O Mode, this signal is used to read the CIS and conguration registers.
-ATA SEL
(True IDE Mode)
To enable True IDE Mode this input should be grounded by the host.
READY
(PC Card Memory Mode)
O37
In Memory Mode, this signal is set high when the CompactFlash Storage Card or CF+
Card is ready to accept a new data transfer operation and is held low when the card is busy.
At power up and at Reset, the READY signal is held low (busy) until the CompactFlash
Storage Card or CF+ Card has completed its power up or reset function. No access of any
type should be made to the CompactFlash Storage Card or CF+ Card during this time.
Note, however, that when a card is powered up and used with RESET continuously
disconnected or asserted, the Reset function of the RESET pin is disabled. Consequently,
the continuous assertion of RESET from the application of power shall not cause the
READY signal to remain continuously in the busy state.
-IREQ
(PC Card I/O Mode)
I/O Operation – After the CompactFlash Storage Card or CF+ Card has been congured
for I/O operation, this signal is used as -Interrupt Request. This line is strobed low to
generate a pulse mode interrupt or held low for a level mode interrupt.
INTRQ
In True IDE Mode signal is the active high Interrupt Request to the host.
Signal Name
Dir.
Pin
Description
-REG
(PC Card Memory Mode)
Attribute Memory Select
I44
This signal is used during Memory Cycles to distinguish between Common Memory and
Register (Attribute) Memory accesses. High for Common Memory, Low for Attribute Memory.
-REG
(PC Card I/O Mode)
The signal shall also be active (low) during I/O Cycles when the I/O address is on the Bus.
-DMACK
(True IDE Mode)
This is a DMA Acknowledge signal that is asserted by the host in response to DMARQ to
initiate DMA transfers.
While DMA operations are not active, the card shall ignore the -DMACK signal, including a
oating condition.
If DMA operation is not supported by a True IDE Mode only host, this signal should be
driven high or connected to VCC by the host.
A host that does not support DMA mode and implements both PCMCIA and True-IDE modes
of operation need not alter the PCMCIA mode connections while in True-IDE mode as long
as this does not prevent proper operation all modes.
Signal Description (con'd)
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