參數(shù)資料
型號(hào): uPSD3212C
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核和16Kbit的SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的的閃存可編程系統(tǒng)器件)
文件頁數(shù): 141/151頁
文件大小: 1194K
代理商: UPSD3212C
141/151
uPSD3212C, uPSD3212CV
Figure 74. Reset (RESET) Timing
Table 113. Reset (RESET) Timing (5V Devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
Table 114. Reset (RESET) Timing (3V Devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
Table 115. V
STBYON
Definitions Timing (5V Devices)
Symbol
Note: 1. V
STBYON
timing is measured at V
CC
ramp rate of 2ms.
Table 116. V
STBYON
Timing (3V Devices)
Symbol
Note: 1. V
STBYON
timing is measured at V
CC
ramp rate of 2ms.
Symbol
Parameter
Conditions
Min
Max
Unit
t
NLNH
RESET Active Low Time
(1)
150
ns
t
NLNH–PO
Power-on Reset Active Low Time
1
ms
t
OPR
RESET High to Operational Device
120
ns
Symbol
Parameter
Conditions
Min
Max
Unit
t
NLNH
RESET Active Low Time
(1)
300
ns
t
NLNH–PO
Power-on Reset Active Low Time
1
ms
t
OPR
RESET High to Operational Device
300
ns
Parameter
Conditions
Min
Typ
Max
Unit
t
BVBH
V
STBY
Detection to V
STBYON
Output High
(Note
1)
20
μs
t
BXBL
V
STBY
Off Detection to V
STBYON
Output
Low
(Note
1)
20
μs
Parameter
Conditions
Min
Typ
Max
Unit
t
BVBH
V
STBY
Detection to V
STBYON
Output High
(Note
1)
20
μs
t
BXBL
V
STBY
Off Detection to V
STBYON
Output
Low
(Note
1)
20
μs
tNLNH-PO
Power-On Reset
tOPR
AI07437
RESET
tNLNH
Warm Reset
tOPR
V
CC
V
CC
(min)
相關(guān)PDF資料
PDF描述
uPSD3212CV Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3212 Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器件)
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