參數(shù)資料
型號(hào): UC3524DTR
廠商: Texas Instruments, Inc.
英文描述: Advanced Regulating Pulse Width Modulators
中文描述: 高級(jí)調(diào)節(jié)脈沖寬度調(diào)制器
文件頁(yè)數(shù): 5/8頁(yè)
文件大?。?/td> 326K
代理商: UC3524DTR
5
UC1524
UC2524
UC3524
Oscillator
The oscillator controls the frequency of the UC1524 and is
programmed by R
T
and C
T
according to the approximate
formula:
1.18
f
R C
T
where
where
where
R
T
is in k
C
T
is in mF
f is in kHz
Practical values of C
T
fall between 0.001mF and 0.1mF.
Practical values of R
T
fall between 1.8k
and 100k
.
This results in a frequency range typically from 120Hz to
500kHz.
Blanking
The output pulse of the oscillator is used as a blanking
pulse at the output. This pulse width is controlled by the
value of C
T
. If small values of C
T
are required for fre-
quency control, the oscillator output pulse width may still
be increased by applying a shunt capacitance of up to
100pF from pin 3 to ground. If still greater dead-time is re-
quired, it should be accomplished by limiting the maxi-
mum duty cycle by clamping the output of the error
amplifier. This can easily be done with the circuit in Fig-
ure 1:
Synchronous Operation
When an external clock is desired, a clock pulse of ap-
proximately 3V can be applied directly to the oscillator
output terminal. The impedance to ground at this point is
approximately 2k
. In this configuration R
T
C
T
must be
selected for a clock period slightly greater than that of the
external clock.
If two or more UC1524 regulators are to operated synchro-
nously, all oscillator output terminals should be tied to-
gether, all C
T
terminals connected to single timing capacitor,
and the timing resistor connected to a single R
T
, terminal.
The other R
T
terminals can be left open or shorted to V
REF
.
Minimum lead lengths should be used between the C
T
ter-
minals.
APPLICATION INFORMATION
16
V
REF
COMP
5k
9
GND
8
1N916
Figure 1. Error amplifier clamp.
Figure 2. Single-ended LC switching regulator circuit.
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