參數(shù)資料
型號: UC3524DTR
廠商: Texas Instruments, Inc.
英文描述: Advanced Regulating Pulse Width Modulators
中文描述: 高級調(diào)節(jié)脈沖寬度調(diào)制器
文件頁數(shù): 3/8頁
文件大小: 326K
代理商: UC3524DTR
3
UC1524
UC2524
UC3524
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for T
A
= –55°C to +125°C
for the UC1524, –25°C to +85°C for the UC2524, and 0°C to +70°C for the UC3524, V
IN
= 20V, and f = 20kHz,
T
A
= T
J.
PARAMETER
TEST CONDITIONS
UC1524/UC2524
MIN
UC3524
UNITS
MAX
MIN
MAX
Error Amplifier Section (cont.)
Common Mode Rejection Ratio T
J
= 25°C
Small Signal Bandwidth
Output Voltage
Comparator Section
Duty-Cycle
Input Threshold
70
3
70
3
dB
MHz
V
A
V
= 0dB, T
J
= 25°C
T
J
= 25°C
0.5
3.8
0.5
3.8
% Each Output On
Zero Duty-Cycle
Maximum Duty-Cycle
0
45
0
45
%
V
V
μ
A
1
1
3.5
1
3.5
1
Input Bias Current
Current Limiting Section
Sense Voltage
Pin 9 = 2V with Error Amplifier
Set for Maximum Out, T
J
= 25°C
190
200
210
180
200
220
mV
Sense Voltage T.C.
Common Mode Voltage
0.2
0.2
mV/°C
V
T
J
= –55°C to 85°C
for the –1V to 1V Limit
T
J
= 125°C
–1
+1
–1
+1
–0.3
+1
V
Output Section (Each Output)
Collector-Emitter Voltage
Collector Leakage Current
Saturation Voltage
Emitter Output Voltage
Rise Time
Fall Time
Total Standby Current (Note)
40
40
V
μ
A
V
V
μ
s
μ
s
mA
V
CE
= 40V
I
C
= 50mA
V
IN
= 20V
R
C
= 2k
, T
J
= 25°C
R
C
= 2k
, T
J
= 25°C
V
IN
= 40V
0.1
1
18
0.2
0.1
8
50
2
0.1
1
18
0.2
0.1
8
50
2
17
17
10
10
The UC1524 is a fixed-frequency pulse-width-modulation
voltage regulator control circuit. The regulator operates at
a frequency that is programmed by one timing resistor
(R
T
), and one timing capacitor (C
T
), R
T
establishes a
constant charging current for C
T
. This results in a linear
voltage ramp at C
T
, which is fed to the comparator provid-
ing linear control of the output pulse width by the error
amplifier. The UC1524 contains an on-board 5V regulator
that serves as a reference as well as powering the
UC1524’s internal control circuitry and is also useful in
supplying external support functions. This reference volt-
age is lowered externally by a resistor divider to provide a
reference within the common-mode range of the error
amplifier or an external reference may be used. The
power supply output is sensed by a second resistor di-
vider network to generate a feedback signal to the error
amplifier. The amplifier output voltage is then compared
to the linear voltage ramp at C
T
. The resulting modulated
pulse out of the high-gain comparator is then steered to
the appropriate output pass transistor (Q
1
or Q
2
) by the
pulse-steering flip-flop, which is synchronously toggled by
the oscillator output. The oscillator output pulse also
serves as a blanking pulse to assure both outputs are
never on simultaneously during the transition times. The
width of the blanking pulse is controlled by the valve of
C
T
. The outputs may be applied in a push-pull configura-
tion in which their frequency is half that of the base oscil-
lator, or paralleled for single-ended applications in which
the frequency is equal to that of the oscillator. The output
of the error amplifier shares a common input to the com-
parator with the current limiting and shutdown circuitry
and can be overridden by signals from either of these in-
puts. This common point is also available externally and
may be employed to control the gain of, or to compen-
sate, the error amplifier or to provide additional control to
the regulator.
PRINCIPLES OF OPERATION
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