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參數(shù)資料
| 型號(hào)： | UC2879L |
| 英文描述： | 350 to 400 MHz FSK/ASK receiver (ST-RECORD01 family) |
| 中文描述： | 電流/電壓模式開關(guān)電源控制器 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 373K |
| 代理商： | UC2879L |
5
UC1879
UC2879
UC3879
PIN DESCRIPTIONS
CLKSYNC
(Bi-directional Clock and Synchronization):
Used as an output, CLKSYNC provides a clock signal. As
an input, this pin provides a synchronization point.
Multiple UC3879s, each with their own local oscillator
frequency, may be connected together by the CLKSYNC
pin, and they will synchronize to the fastest oscillator.
This pin may also be used to synchronize the UC3879 to
an external clock, provided the frequency of the external
signal is higher than the frequency of the local oscillator.
CLKSYNC is internally connected to an emitter follower
pull-up and a current source pull-down (300
μ
A typical).
Therefore an external resistor to GND can be used to
improve the CLKSYNC pin’s ability to drive capacitive
loads.
COMP
(Error Amplifier Output): This pin is the output of
the gain stage for overall feedback control. Error amplifier
output voltage levels below 0.9 volt forces zero phase
shift. Since the error amplifier has a relatively low current
drive capability, the output may be overridden by driving it
with a sufficiently low impedance source.
CT
(Oscillator Frequency Set): After choosing RT to set
the required upper end of the linear duty cycle range, the
timing capacitor (CT) value is calculated to set the
oscillator frequency as follows:
CT
Dlin
RT
f
=
1 08
.
Connect the timing capacitor directly between CT and
GND. Use a high quality ceramic capacitor with low ESL
and ESR for best results. A minimum CT value of 200pF
insures good accuracy and less susceptibility to circuit
layout parasitics. The oscillator and PWM are designed to
provide practical operation to 600kHz.
CS
(Current Sense): This pin is the non-inverting input to
the two current fault comparators whose references are
set internally to fixed values of 2.0V and 2.5V. When the
voltage at this pin exceeds 2.0V, and the error amplifier
output voltage exceeds the voltage on the ramp input, the
phase shift limiting overcurrent comparator will limit the
phase shifting on a cycle-by-cycle basis. When the
voltage at this pin exceeds 2.5V, the current fault latch is
set, the outputs are forced OFF, and a soft start cycle is
initiated. If a constant voltage above 2.5V is applied to
this pin the outputs are disabled and held low. When CS
is brought below 2.5V, the outputs will begin switching at
0 degrees phase shift before the SS pin begins to rise.
This condition will not prematurely deliver power to the
load.
DELSETA-B, DELSETC-D
(Output Delay Control): The
user programmed currents from these pins to GND set
the turn on delay for the corresponding output pair. This
delay is introduced between the turn off of one switch
and the turn on of another in the same leg of the bridge
to allow resonant switching to take place. Separate
delays
are
provided
for
accommodate differences in the resonant capacitor
charging currents.
the
two
half-bridges
to
EA–
(Error Amplifier Inverting Input): This is normally
connected to the voltage divider resistors which sense
the
power
supply
output
compensation components are connected between this
pin and COMP.
voltage
level. The
loop
GND
(Signal Ground): All voltages are measured with
respect to GND. The timing capacitor on CT, and bypass
capacitors on VREF and VIN should be connected
directly to the ground plane near GND.
OUTA – OUTD
(Outputs A-D): The outputs are 100mA
totem pole output drivers optimized to drive FET driver
ICs. The outputs operate as pairs with a nominal 50%
duty cycle. The A-B pair is intended to drive one
half-bridge
in
the
external
synchronized to the clock waveform. The C-D pair drives
the other half-bridge with switching phase shifted with
respect to the A-B outputs.
power
stage
and
is
PWRGND
(Power Ground): VC should be bypassed with
a ceramic capacitor from VC to the section of the ground
plane that is connected to PWRGND. Any required bulk
reservoir capacitor should be connected in parallel.
PWRGND and GND should be connected at a single
point near the chip to optimize noise rejection and
minimize DC voltage drops.
RAMP
(Voltage Ramp): This pin is the input to the PWM
comparator. Connect it to CT for voltage mode control.
For current mode control, connect RAMP to CS and also
to the output of the current sense transformer circuit.
Slope compensation can be achieved by injecting a
portion of the ramp voltage from CT to RAMP.
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UC2879N | 350 to 400 MHz FSK/ASK receiver (ST-RECORD01 family) |
| UC2879Q | 40MHZ to 1GHZ amplifier |
| UC3879DW | Quad 2-input OR gate |
| UC3879N | Octal D-type latch with 3 state outputs (non inverted) |
| UC3879Q | Octal D-type flip-flop with 3 state outputs (non inverted) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UC2879N | 功能描述:軟開關(guān) PWM 控制器 Phase Shift Resonant Controller RoHS:否 制造商:Fairchild Semiconductor 輸出端數(shù)量: 輸出電流: 開關(guān)頻率: 工作電源電壓:30 V 電源電流: 最大工作溫度:+ 105 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Reel |
| UC2879NG4 | 功能描述:軟開關(guān) PWM 控制器 Phase Shift Resonant Controller RoHS:否 制造商:Fairchild Semiconductor 輸出端數(shù)量: 輸出電流: 開關(guān)頻率: 工作電源電壓:30 V 電源電流: 最大工作溫度:+ 105 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Reel |
| UC2886D | 功能描述:電流型 PWM 控制器 Avg Current Mode IC RoHS:否 制造商:Texas Instruments 開關(guān)頻率:27 KHz 上升時(shí)間: 下降時(shí)間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| UC2886DG4 | 功能描述:電流型 PWM 控制器 Avg Current Mode IC RoHS:否 制造商:Texas Instruments 開關(guān)頻率:27 KHz 上升時(shí)間: 下降時(shí)間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| UC28TRXS | 制造商:ST MICRO 功能描述:New |
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