
4
UC1879
UC2879
UC3879
Note 1.
Phase shift percentage (0% = 0
°
, 100% = 180
°
) is de-
fined as
θ =
200
T
where
θ
is the phase shift, and
Φ
and T are defined in Figure 1.
At 0% phase shift,
Φ
is the output skew.
Φ
%
Note 2.
Delay time is defined as:
delay
T
duty cycle
=
1
where T is defined in Figure 1.
Note 3.
Ramp offset voltage has a temperature coeffecient of
about –4mV/
°
C.
Note 4.
The zero phase shift voltage is the voltage measured
at COMP which forces zero phase shift. This condition corre-
sponds to zero effective output power. Zero phase shift voltage
has a temperature coeffecient of about –2mV/
°
C.
Note 5.
Delay time can be programmed via resistors from the
delay set pins to ground.
(
)
Delay Time
R
DELAY
=
0 89 10
10
.
sec
The recommended range for R
DELAY
is 1.9k to 10k.
Figure 1. Phase Shift, Output Skew & Delay Time
Definitions
Duty Cycle =
t
T
Period = T
T
DHL
(A to C) = T
DHL
(B to D) =
Φ
ELECTRICAL CHARACTERISTICS
Unless specified; VC = VIN = V
UVSEL
=12V, CT = 470pF, RT = 9.53k, R
DELSETA-B
=
R
DELSEC-D
= 4.8k, C
DELSETA-B
= C
DELSETC-D
= 0.01
μ
F, T
A
= T
J
.
PARAMETER
TEST CONDITIONS
Ramp Peak Voltage
Current Limit
Input Bias
V
CS
= 3.0V
Threshold Voltage
Delay to OUTA, B, C, D
Cycle-by-Cycle Current Limit
Input Bias
V
CS
= 2.2V
Threshold Voltage
Delay to Output Zero Phase
Soft Start/Reset Delay
Charge Current
V
SS
= 0.5V
Discharge Current
V
SS
= 1V
Restart Threshold
Discharge Level
Output Drivers
Output Low Level
I
OUT
= 10mA
Output High Level
I
OUT
= –10mA, Referenced to VC
Delay Set (Note 5)
Delay Time
R
DELSETA-B
= R
DELSETC-D
= 4.8k
Delay Time
R
DELSETA-B
= R
DELSETC-D=
1.9k
Zero Delay
V
DELSETA-B
= V
DELSETC-D
= 5V
MIN
2.8
TYP
2.9
MAX
3.2
UNITS
V
2
10
2.65
300
μ
A
V
ns
2.35
2.5
160
2
2
10
2.15
300
μ
A
V
ns
1.85
110
–20
120
4.3
–9
230
4.7
300
–3
μ
A
μ
A
V
mV
0.3
2.2
0.4
3
V
V
300
130
430
170
5
600
250
ns
ns
ns
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