參數(shù)資料
型號(hào)： TWL2214CA
英文描述： High voltage fast-switching NPN power transistor
中文描述： 電源管理IC和鋰離子電池充電控制
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 511K
代理商： TWL2214CA
SLVS321A
–
OCTOBER 2001
–
REVISED JANUARY 2002
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics, T
A
=
–
25
°
C to 85
°
C (unless otherwise noted) (continued)
battery charger control (continued)
PARAMETER
TEST CONDITIONS
VBREG
= 4.1 V
VBREG = 4.2 V
MIN
4.059
TYP
4.1
MAX
4.141
UNIT
VBAT regulation (CV)
reg lation (CV)
V
4.158
4.2
4.242
Low voltage cutoff
1.9
High voltage cutoff
4.45
VBAT
Fast charge voltage
3.2
V
Precharge voltage
(see Note 5)
1.9
2.05
2.2
Pack wake-up voltage
4.214
4.30
4.386
ICC
VBREG is the regulated battery voltage programmed by setting bit 1 of CSV register.
Operating current
20
mA
NOTES:
5. Precharge current set by IPRE
VPRE
RPR
45
where VPRE
1.2 V
10%
ADC specification
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
Output impedance <100 k
Confirm monotonous (see Note 6)
8
bit
Integral nonlinearity
–
1
1
LSB
Low-level input
ADC output = 00H
0
0.1
V
High-level input
ADC output = FFH
1.9
2
2.1
V
Input capacitance
3
pF
ADC CLK
450
500
550
kHz
AD conversion time, tC
Power-up time
From the start of SETUP
16
CLK
μ
s
From the ADEN up selection
10
NOTE 6:
LSB
2V
255
7.8 mV
DISB interface
The TWL2214CA device supports both I
2
C bus and SPI bus serial interfaces. The interface uses serial data
(DATA) and serial clock (CLK) to carry information between the devices. The CE terminal (A8) in the GQE
package selects I
2
C or SPI. The device that initiates a transfer, generates clock signals, and terminates a
transfer is the master. The TWL2214CA device operates as a slave device. The slave address for this device
is fixed at E4h for write operations and E5h for read operations. The LSB of this slave address is simply an R/W
flag. DATA is a bidirectional line connected to V
REG1
via a 10-k
pullup resistor. Data can be transferred at a
rate up to 400K bits/s for I
2
C and up to 2M bits/s for SPI with one clock pulse generated for each data bit
transferred. MSB is transferred first. When the bus is free, both DATA and CLK are high. Data transfer can only
be initiated when the bus is free. The bus must return to the free state when the transfer is complete. Failure
to return to the free state may cause an error.
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