參數(shù)資料
型號(hào): TW9903
廠商: Electronic Theatre Controls, Inc.
英文描述: TW9903 ? Multi-standard Video Decoder With High Quality Down Scaler
中文描述: TW9903?多標(biāo)準(zhǔn)視頻解碼器,高品質(zhì)下倍線器
文件頁數(shù): 51/74頁
文件大小: 630K
代理商: TW9903
TW9903
TECHWELL, INC.
51
REV. 0.92 ( B )
06/02/2002
0x1F – Test Control Register (TEST)
Bit
Function
R/W
Description
Reset
7-0
TEST
R/W This register is reserved for testing purpose. In normal operation,
only 0 should be written into this register.
1 = Analog test mode. Y and C channel portion of the device can
be tested in this mode. The Y channel ADC output can be obtained
from HACTIVE, HSYNC and VD[15:8] for bit1, bit0 and bit9-2,
respectively. The C channel ADC output can be obtained from
VACTIVE, VSYNC and VD[7:0] for bit1, bit0 and bit9-2,
respectively.
2 = Digital test mode1. The sync portion of the device should be
tested in this mode. The 8-bit input corresponds to TISVN, TEST1,
TEST2, TDO, TCK, TRST#, TMS, and TDI in the order of bit 7 to 0.
3 = Analog test mode 1. It is same as the previous analog test
mode except that the C channel ADC inputs come from TADCP
and TADCN instead of C_PBIN.
4 = Digital test mode 2. In addition to digital test mode 1, this test
mode allows the C channel data to be inputted from VD[7:0]. In this
mode, only 8-bit output format is allowed.
5 = Closed Caption test mode.
6 = Analog test mode 2. The “C channel portion of the device can
be tested in this mode. The C channel ADC output can be
obtained from VACTIVE, VSYNC and VD[7:0] for bit1, bit0 and
bit9-2, respectively.
7 = Analog DAC output mode. The 6-bit Sync output corresponds
to TDI, TMS, TRST#, TCK, TISVN and TDO in the order of bit 5 to
0. Y and Cb/Cr outputs correspond to VD[15:8] and VD[7:0],
respectively. In this mode, HACTIVE pin will be BGOUT and
VACTIVE pin will be VSDLY.
0
0x20 – Clamping Gain (CLMPG)
Bit
Function
R/W
Description
Reset
7-4
CLPEND
R/W These 4 bits set the end time of the clamping pulse in the
increment of 8 system clocks. The clamping time is determined by
this together with CLPST.
A
3-0
CLPST
R/W These 4 bits set the start time of the clamping pulse in the
increment of 8 system clocks. It is referenced to PCLAMP position.
0
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