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參數(shù)資料
| 型號： | TW9903 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | TW9903 ? Multi-standard Video Decoder With High Quality Down Scaler |
| 中文描述： | TW9903？多標準視頻解碼器，高品質(zhì)下倍線器 |
| 文件頁數(shù)： | 29/74頁 |
| 文件大?。?/td> | 630K |
| 代理商： | TW9903 |
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TW9903
TECHWELL, INC.
29
REV. 0.92 ( B )
06/02/2002
SDAT is the data line. Both lines are pulled high by resistors connected to VDD. ICs communicate
on the bus by pulling SCLK and SDAT low through open drain outputs. In normal operation the
master generates all clock pulses, but control of the SDAT line alternates back and forth between
the master and the slave. For both read and write, each byte is transferred MSB first, and the data
bit is valid whenever SCLK is high.
The TW9903 is operated as a bus slave device. It can be programmed to respond to one of two 7-
bit slave device addresses by tying the SIAD (Serial Interface ADdress) pin ether to VDD or GND
(See Table 5.). If the SIAD pin is tied to VDD, then the least significant bit of the 7-bit address is a
“1”. If the SIAD pin is tied to GND then the least significant bit of the 7-bit address is a “0”. The most
significant 6-bits are fixed. The 7-bit address field is concatenated with the read/write control bit to
form the first byte transferred during a new transfer. If the read/write control bit is high the next byte
will be read from the slave device. If it is low the next byte will be a write to the slave. When a bus
master (the host microprocessor) drives SDA from high to low, while SCL is high, this is defined to
be a start condition (See Figure 15.). All slaves on the bus listen to determine when a start
condition has been asserted.
After a start condition, all slave devices listen for the their device addresses. The host then sends a
byte consisting of the 7bit slave device ID and the R/W bit. This is shown in Figure 16. (For the
TW9903, the next byte is normally the index to the TW9903 registers and is a write to the TW9903
therefore the first R/W bit is normally low.)
After transmitting the device address and the R/W bit, the master must release the SDAT line while
holding SCLK low, and wait for an acknowledgement from the slave. If the address matches the
device address of a slave, the slave will respond by driving the SDAT line low to acknowledge the
condition. The master will then continue with the next 8-bit transfer. If no device on the bus
responds, the master transmits a stop condition and ends the cycle. Notice that a successful
transfer always includes nine clock pulses.
To write to the internal register of theTW9903, the master sends another 8bits of data, the
TW9903 loads this to the register pointed by the internal index register. The TW9903 will
acknowledge the 8bit data transfer and automatically increment the index in preparation for the
next data. The master can do multiple writes to the TW9903 if they are in ascending sequential
order. After each 8bit transfer the TW9903 will acknowledge the receipt of the 8bits with an
acknowledge pulse. To end all transfers to the TW9903 the host will issue a stop condition.
Serial Bus Interface 7-bit Slave Address
Read/Write
bit
1=Read
0=Write
1
0
0
0
1
SIAD1
SIAD0
Table 5 TW9903 serial bus interface 7-bit slave address and read write bit
A TW9903 read cycle has two phases. The first phase is a write to the internal index register. The
second phase is the read from the data register. (See figure 16). The host initiates the first phase
by sending the start condition. It then sends the slave device ID together with a 0 in the R/W bit
position. The index is then sent followed by either a stop condition or a second start condition. The
second phase starts with the second start condition. The master then resends the same slave
device ID with a 1 in the R/W bit position to indicate a read. The slave will transfer the contents of
the desired register. The master remains in control of the clock. After transferring eight bits, the
slave releases and the master takes control of the SDAT line and acknowledges the receipt of data
to the slave. To terminate the last transfer the master will issue a negative acknowledge (SDAT is
left high during a clock pulse) and issue a stop condition.
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相關(guān)代理商/技術(shù)參數(shù) |
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| TW9903-FB | 功能描述:IC DECODER VIDEO NTSC/PAL/SECAM RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TW9903-MB | 功能描述:IC DECODER VIDEO NTSC/PAL/SECAM RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TW9903-MBS | 功能描述:IC NTSC/PAL/SECAM DECODR 100PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TW9905-FD | 功能描述:IC DECODER VIDEO NTSC/PAL/SECAM RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TW9905-MD | 功能描述:IC DECODER VIDEO NTSC/PAL/SECAM RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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