參數(shù)資料
型號(hào): TW9903
廠商: Electronic Theatre Controls, Inc.
英文描述: TW9903 ? Multi-standard Video Decoder With High Quality Down Scaler
中文描述: TW9903?多標(biāo)準(zhǔn)視頻解碼器,高品質(zhì)下倍線器
文件頁(yè)數(shù): 13/74頁(yè)
文件大小: 630K
代理商: TW9903
TW9903
TECHWELL, INC.
13
REV. 0.92 ( B )
06/02/2002
HSYNC, VSYNC and FIELD
The HSYNC and VSYNC output timing is VMI v1.4 compliant. The leading edge of HSYNC depends
on the input video signal. The pulse width of HSYNC is programmable from 8-128 CLKX1 cycles. The
leading edge of VSYNC also depends on the video input. It typically occurs on the low period of first
serration pulse of the video signal. The trailing edge of VSYNC follows the HSYNC in order to be VMI
compliant. For the start of the odd field, it occurs 64 CLKX2 cycles after the trailing edge of HSYNC that
follows the last equalization pulse of the input. For the indication of the even field, the trailing edge of
VSYNC occurs 64 CLKX2 cycles after the leading edge of HSYNC that follows the last equalization
pulse of the input. In this latter case, the HSYNC width has to be set at least 64 CLKX1 cycles. The
FIELD output indicates the input vdeo source field state as determined by the decoder. It changes
state at the leading edge of VSYNC to reflect the state of following field. If the field cannot be
determined due to video source noise, it will toggle its state for each field until it can be corrected by the
source. Figure4 shows HSYNC output timing. HSYNC changes when CLKX1 goes high. Figure 5a
shows Odd field VSYNC and HSYNC Timing. Figure 5b shows Even field VSYNC and HSYNC timing.
Figure 6 shows FIELD and VSYNC Timing. The leading edge of VSYNC changes with FIELD signal.
The video timing of these outputs is also illustrated in Figure 7a and 4b.
Figure 4 HSYNC output timing
Fgure 5a. Odd field VSYNC and HSYNC timing
Figure 5b. Even field VSYNC and HSYNC timing
C L K X 2
C L K X 1
HSYNC
Changed by HSLEN
FIELD(0)
H S Y N C
V S Y N C
64 CLKX2 Clocks
FIELD(1)
H S Y N C
V S Y N C
64 CLKX2 Clocks
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