- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373745 > TSS463A-TERZ (Atmel Corp.) VAN Data Link Controller with Serial Interface PDF資料下載
參數(shù)資料
| 型號： | TSS463A-TERZ |
| 廠商： | Atmel Corp. |
| 英文描述： | VAN Data Link Controller with Serial Interface |
| 中文描述： | 凡數(shù)據(jù)與串行接口鏈路控制器 |
| 文件頁數(shù)： | 7/60頁 |
| 文件大?。?/td> | 816K |
| 代理商： | TSS463A-TERZ |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
7
TSS463-AA
4205B–AUTO–12/04
Figure 4.
CPOL and CPHA in the TSS463AA
At the beginning of a transmission over the serial interface, the first byte is the address
of the TSS463AA register to be accessed. The next byte transmitted is the control byte
which determines the direction of the communication. The following bytes are data bytes
(consecutive bytes are written in or read from Address, Address + 1, Address + 2,...,
Address + n with n = 0 to 28).
To make sure the TSS463AA is not out of synchronization, the SPI interface will trans-
mit data “0xAA" and "0x55” on the MISO pin during address and control byte time. This
way, the master always ensures the TSS463AA is well-synchronized. If the TSS463AA
is out of synchronization, the master can assert the SS pin inactive to re synchronize the
SPI interface or can assert the RESET pin active or can send an initialization sequence.
When the SS pin is inactive, the SCLK is allowed to toggle. This will have no effect on
the TSS463AA SPI module.
SPI Control Byte
The SPI control byte is transmitted by the master (CPU) to the TSS463AA. It specifies
whether it is a TSS463AA Write or Read.
Table 1.
SPI Control Byte
DIR: Serial Transfer Direction
Zero
: Read Operation. The data bytes will be read by the master (CPU) from the
TSS463AA.
One
: Write Operation. The data bytes will be written by the master (CPU) to the
TSS463AA.
In both cases, address auto-increment mechanism will take place when more than one
data byte is read or written. This mechanism is inhibited when address value reaches
0xFF.
The seven following bits are reserved and must be equal to: 1100000.
When the master (CPU) conducts a write, it sends an address byte, a control byte and
data bytes on its MOSI line. The slave device (TSS463AA) will send, if well-synchro-
nized, “0xAA” during the address byte and “0x55” during the control byte on its MISO
line.
0x55
SCLK
MOSI
SS
SPI 8 Pulses
Data Transmit Points
Data Sample Points
CPOL = CPHA = 1
MISO
0x66
7
6
5
4
3
2
1
0
DIR
1
1
0
0
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSS463C | VAN Data Link Controller with Serial Interface |
| TSS4B02G | Single Phase 4.0 Amps. Glass Passivated Super Fast Bridge Rectifiers |
| TSS4B03G | Single Phase 4.0 Amps. Glass Passivated Super Fast Bridge Rectifiers |
| TSS4B01G | Single Phase 4.0 Amps. Glass Passivated Super Fast Bridge Rectifiers |
| TSS5G45S | TOSHIBA SOLID STATE AC RELAY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSS463B | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Serial VAN Data Link Controller |
| TSS463B_03 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Serial VAN Data Link Controller |
| TSS463B_04 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:VAN Data Link Controller with Serial Interface |
| TSS463B-TERA | 制造商:Temic 功能描述:LAN Node Controller, 16 Pin, SOP |
| TSS463B-TERA-9 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:VAN Data Link Controller with Serial Interface |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。