參數(shù)資料
型號(hào)： TPIC74100QPWPRQ1
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： 2.5 A SWITCHING REGULATOR, 440 kHz SWITCHING FREQ-MAX, PDSO20
封裝： GREEN, PLASTIC, HTSSOP-20
文件頁(yè)數(shù)： 4/30頁(yè)
文件大?。?/td> 781K
代理商： TPIC74100QPWPRQ1
www.ti.com
Extension of the Input Voltage Range on V(driver)
Low-Power Mode
Temperature and Short-Circuit Protection
Switch Output Terminal (5Vg) Current Limitation
Soft Start
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
The switch timings of transistors Q1 and Q2 are not considered. In boost mode, the logical control of the
transistors does not change.
To ensure a stable 5-V output voltage with the output load in the specified range, the V(driver) supply must be
greater than or equal to 5 V for greater than 1 ms (typical). After a period of 1 ms (typical), the logic may be
supplied by the VOUT regulator and the V(driver) supply may be capable of operating down to 1.5 V.
The switch-mode regulator does not start at V(driver) less than 5 V.
To reduce quiescent current and to provide efficient operation, the regulator enters a pulsed mode.
The device enters this mode by a logic-level low on this terminal.
Automatic low-power mode is not available.The low-power-mode function is not available in boost mode. The
device leaves low-power mode during boost mode regardless of the logic level on the CLP terminal.
To prevent thermal destruction, the device offers overtemperature protection to disable the IC. Also, short-circuit
protection is included for added protection on VOUT and 5Vg.
A charge pump drives the internal FET, which switches the primary output voltage VOUT to the 5Vg pin.
Protection is implemented to prevent the output voltage from dropping below its specified value while enabling
the secondary output voltage. An explanation of the block diagram (see Figure 1) is given by the following
example:
Device is enabled, output voltage V
OUT is up and stable.
5Vg is enabled (pin 5Vg_ENABLE set to high) with load resistance connected to 5Vg pin.
If output voltage V
OUT drops below typical ( VOUT – 100 mV), the charge pump of the 5Vg FET is switched off
and the FET remains on for a while as the gate voltage drops slowly.
If V
OUT drops below the RESET threshold of 4.65 V (typical), the FET of the secondary output voltage 5Vg is
switched off (gate drawn to ground level).
A deglitch time ensures that a device reset does not occur if V
OUT drops to the reset level during the 5Vg
turnon phase.
If V
OUT rises above typical (VOUT – 100 mV), the charge pump of the 5Vg FET is switched on and drives the
gate of the 5Vg FET on.
On power up, the device offers a soft-start feature which ramps the output of the regulator at a slew of 10 V/ms.
When a reset occurs, the soft start is reenabled. Additionally, if the output capacitor is greater than 220 F
(typical), the slew rate decreases to a value set by the internal current limit. In boost mode, the soft-start feature
is not active.
12
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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