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參數(shù)資料
| 型號： | TPIC43T02DAR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, PDSO38 |
| 封裝： | PLASTIC, TSSOP-38 |
| 文件頁數(shù)： | 7/29頁 |
| 文件大小： | 463K |
| 代理商： | TPIC43T02DAR |
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TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
rotor position sensing/commutation control
To electronically commutate the three phases, the state of the three Hall-effect sensors is decoded to drive the
correct phases based on desired motor rotational direction and rotor position. This is accomplished by decoding
the Hall sensor gray-code with the F/R input condition as described in Table 3. If all three Hall inputs are detected
as identical states, this is an illegal condition and the device turns all outputs OFF.
Table 3. Hall Position Sensor Input Gray-Code Logic
COMMUTATION
F/R = LOW
F/R = HIGH
PHASE A
PHASE B
PHASE C
STEP
IN1
IN2
IN3
IN1
IN2
IN3
UPPER
LOWER
UPPER
LOWER
UPPER
LOWER
A
L
H
L
PWM
Note 4
ON
B
L
H
L
PWM
Note 4
ON
C
L
H
L
H
L
H
PWM
Note 4
ON
D
H
L
H
ON
PWM
Note 4
E
H
L
H
ON
PWM
Note 4
F
H
L
H
L
H
L
ON
PWM
Note 4
Illegal
L
all OFF
Illegal
H
all OFF
NOTE 4: For the Half-H in which GUx is being switched by PWM, the complimentary LGx can be EEPROM programmed by a single bit to enable
or disable synchronous rectification during t(OFF) of each PWM cycle. This allows configuration of the device for applications where
synchronous rectification can or cannot be used.
digital PWM operation
In Table 3, the term PWM represents the pulse-width-modulation duty-cycle. PWM switching is implemented
with the upper gate drive such that recirculation occurs in the lower external FET during the OFF portion of each
period. Coast mode is enabled or disabled using EEPROM address 0, bit 4. Synchronous rectification mode
is enabled or disabled using EEPROM address 0, bit 3.
An 8-bit digital PWM circuit uses an internal 5.8 Mhz oscillator as an input frequency. Each PWM period is
defined by 255 (28 –1) intervals where the number of ON intervals is controlled by the value of an 8-bit binary
input word from the digital filter output. The PWM generator is implemented such that duty cycle is:
Duty cycle
+
n
28 –1
+ n
255
Where:
n = decimal equivalent of the 8-bit binary input word
coast mode, (EEPROM address 0, bit 4, default = H)
When coast function is enabled (EEPROM address 0, bit 4 = H), the device uses a special mode to control speed
of the motor when it exceeds the selected reference speed. Referring to Figure 10, when FGSOUT frequency
exceeds f(ref) by 5%, resulting in a loss of lock detect, the high-side FET gate drives (UGx) are disabled and the
low-side FET drives (LGx) continue to sequence as per the commutation table. This will continue until FGSOUT
frequency drops below f(ref), which re-enables the high-side gate drives. The coast mode will override
synchronous rectification mode if both are enabled (see following) after the FSGOUT signal exceeds f(ref).
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