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參數(shù)資料
| 型號： | TMS320SA32NL |
| 英文描述： | PCM， Other/Special/Miscellaneous |
| 中文描述： | PCM格式，其他/特別/雜項(xiàng) |
| 文件頁數(shù)： | 45/132頁 |
| 文件大小： | 1707K |
| 代理商： | TMS320SA32NL |
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SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
45
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
ROM
The LC240xA devices contain mask-programmable ROM located in program memory space. Customers can
arrange to have this ROM programmed with contents unique to any particular application. See Table 1 for the
ROM memory capacity of each LC240xA device.
boot ROM (LF240xA only)
Boot ROM is a 256-word ROM memory-mapped in program space 0000
–
00FF. This ROM will be enabled if the
BOOT_EN pin is low during reset. The BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if the BOOT_EN
pin is low at reset. Boot ROM can also be enabled by writing 0 to the SCSR2.3 bit and disabled by writing 1 to
this bit.
The boot ROM has a generic bootloader to transfer code through SCI or SPI ports. The incoming code should
disable the BOOT_ROM bit by writing 1 to bit 3 of the SCSR2 register, or else, the whole Flash array will not
be enabled.
The boot ROM code sets the PLL to x2 or x4 option based on the condition of the SCITXD pin during reset. The
SCITXD pin should be pulled high/low to select the PLL multiplication factor. The choices made are as follows:
If the SCITXD pin is pulled low, the PLL multiplier is set to 2.
If the SCITXD pin is pulled high, the PLL multiplier is set to 4. (Default)
If the SCITXD pin is not driven at reset, the internal pullup selects the default multiplier of 4.
Care should be taken such that a combination of CLKIN and the PLL multiplication factor should not result in
a CPU clock speed of greater than 40 MHz, the maximum rated speed.
Furthermore, when the bootloader is used, only specific values of CLKIN would result in a baud-lock for the SCI.
Refer to the
TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals
(literature
number SPRU357) for more details about the bootloader operation.
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