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參數(shù)資料
| 型號(hào)： | TLC555QDRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 模擬波形發(fā)生器 |
| 英文描述： | PULSE; RECTANGULAR, 1.2 MHz, TIMER, PDSO8 |
| 封裝： | GREEN, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁(yè)數(shù)： | 14/14頁(yè) |
| 文件大?。?/td> | 209K |
| 代理商： | TLC555QDRQ1 |
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APPLICATION INFORMATION
0.1
F
0.1
F
CT
CL
RL
Output
RB
RA
GND
TRIG
THRES
RESET
DISCH
CONT
VDD
OUT
VDD
2/3 VDD
1/3 VDD
GND
tPHL
tPLH
tc(H)
tc(L)
CIRCUIT
TRIGGER AND THRESHOLD VOLTAGE WAVEFORM
TLC555
6
1
3
8
5
4
7
2
t
c(H) [
C
T
(R
A )
R
B
) In 2 (In 2 + 0.693)
t
c(L) [
C
T
R
B
In 2
Period + tc(H) ) tc(L) [ CT (RA ) 2RB) In 2
Output driver duty cycle +
t
c(L)
t
c(H) )
t
c(L)
[ 1 –
R
B
R
A )
2R
B
Output waveform duty cycle +
t
c(H)
t
c(H) )
t
c(L)
[
R
B
R
A )
2R
B
LinCMOS TIMER
SLFS078 – OCTOBER 2006
Figure 3. Astable Operation
Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor CT
charges through RA and RB to the threshold voltage level (approximately 0.67 VDD) and then discharges through
RB only to the value of the trigger voltage level (approximately 0.33 VDD). The output is high during the charging
cycle (tc(H)) and low during the discharge cycle (tc(L)). The duty cycle is controlled by the values of RA, RB, and CT
as shown in the following equations.
The 0.1-
F capacitor at CONT in Figure 3 decreases the period by about 10%.
The formulas shown above do not allow for any propagation delay times from the TRIG and THRES inputs to
DISCH. These delay times add directly to the period and create differences between calculated and actual
values that increase with frequency. In addition, the internal on-state resistance (ron) during discharge adds to RB
to provide another source of timing error in the calculation when RB is very low or ron is very high.
9
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