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參數(shù)資料
| 型號： | TDA8777HL/24 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM PITCH, MS-026, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 87K |
| 代理商： | TDA8777HL/24 |
2004 May 17
6
Philips Semiconductors
Objective specication
Triple 10-bit video DAC
up to 330 Msps
TDA8777
FUNCTIONAL DESCRIPTION
This triple 10-bit video DAC is designed to convert digital
input signals into analog output currents. All inputs (clock,
data, blank and sync) must be TLL levels.
Voltage reference
The voltage reference input to pin VREF should be 1.21 V.
For correct operation, a 100 nF capacitor should be
connected between pin VREF and pin VDDA.
An external reference resistor must be connected between
pin RSET and analog ground. This resistor sets the
reference current which determines the analog output
level, and is specified to be 560
. This value allows a
1 V (p-p) output (video plus sync) into a 37.5
load, such
as a double-terminated 75
coaxial cable.
Blanking and sync pulse insertion
The video signal (see Fig.3) is comprised of the following
three parts:
1. The video information: defined by the 10 bits used to
drive the DAC {(a nominal signal of 700 mV (p-p)}.
2. The sync pulse: a horizontal synchronization (hsync)
pulse indicates the end of a video line and the start of
the next video line (nominal amplitude of 300 mV).
Added to the video signal output via the SYNC input
(active LOW).
3. The blanking period: allows interface-free detection of
both sync and video, blanking is allocated either side
of the sync pulse. The blank level is equal to the video
black level. Added to the video signal output via the
BLANK input (active LOW).
The values of SYNC and BLANK are latched on the rising
edge of the clock signal. When no sync and no blank are
applied, the DAC can be used continuously. This is the
so-called generic mode.
Because the signal delay in the DAC is 1.5 times the clock
period, the sync and blank are also delayed by 1.5 times
the clock period.
handbook, full pagewidth
MLE291
sync pulse
blanking period
video information
0.7 V
0.3 V
Fig.3 Video signal sync pulse and blanking period.
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