參數(shù)資料
型號: TDA7306
廠商: 意法半導(dǎo)體
英文描述: Digital Controlled Stereo Audio Processor(數(shù)控立體聲音頻處理器)
中文描述: 數(shù)控立體聲音頻處理器(數(shù)控立體聲音頻處理器)
文件頁數(shù): 9/13頁
文件大?。?/td> 216K
代理商: TDA7306
APPLICATION INFORMATION
(continued)
SERIALBUS INTERFACE
The
serial bus interface is compatible to MI-
CROWIRE and SPI bus systems.
During the LOW state of the chip enable signal
(CE) the data on pin DA are clocked into the shift
register at the LOW to HIGH transition of the
clocksignal CL.
At the LOW to HIGH transition of the CE signal
the content of the internal shift register is stored
into the addressedlatches.
The transmissionis separatedinto byteswith 8 bit
according to the data specification of the audio-
processor. After every byte a positiveslope of the
CE signal has to be generated in order to store
the data byte.
A special clock counter enables the latch of the
data byte only, if exactly 8 clocks were present
during the LOW state of the CE signal. This re-
sults in a high immunity against spikes on the
clock line and avoids a storage of wrong databy-
tes.
Figure16:
BUSTiming
Nr.
Parameter
Min.
Max.
250
Units
KHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
Clock Frequency
CE Lead time
Clock High Time
Clock Low Time
Data Hold Time
Data Setup Time
Clock Setup Time
CE lagtime
Clock Hold Time
CE High TIme
1
2
3
4
5
6
7
8
9
4
2
2
1.8
1.8
0
0
6
6
TDA7306
9/13
相關(guān)PDF資料
PDF描述
TDA7309D DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS
TDA7309 Digital Controlled Stereo Audio Processor With Loudness(帶響度的數(shù)控立體聲音頻處理器)
TDA7310 Serial Bus Controlled Audio Processor(串行總線控制音頻處理器)
TDA7311 Serial Bus Controlled Audio Processor(串行總線控制音頻處理器)
TDA7312 Digital Controlled Stereo Audio Processor(數(shù)控立體聲音頻處理器)
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