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| 型號： | T83C5101ZZZ-3ZSIL |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PDIP24 |
| 封裝： | DIP-24 |
| 文件頁數(shù)： | 50/52頁 |
| 文件大?。?/td> | 701K |
| 代理商： | T83C5101ZZZ-3ZSIL |
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Rev. F - 12 March, 2001
7
T87C5101
T83C5101/02
7. T8xC5101/02 Enhanced Features
In comparison to the original 80C52, the T8xC5101/02 implements some new features, which are:
The X2 option.
The Dual Data Pointer.
The extended RAM.
The 4 level interrupt priority system.
Some enhanced features are also located in the UART and the timer 2.
7.1. X2 Feature
The T8xC5101/02 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the
following advantages:
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Save power consumption while keeping same CPU power (oscillator power saving).
Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main
clock input of the core (phase generator). This divider may be disabled by software.
7.1.1. Description
The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and
peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,
the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block
diagram. X2 bit is validated on XTAL1
÷2 rising edge to avoid glitches when switching from X2 to STD mode.
Figure 2. shows the mode switching waveforms.
Figure 1. Clock Generation Diagram
XTAL1
2
CKCON reg
X2
state machine: 6 clock cycles.
CPU control
FOSC
FXTAL
0
1
XTAL1:2
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