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參數(shù)資料
| 型號： | T8208 |
| 廠商： | Lineage Power |
| 英文描述： | Asychronous Transfer Mode (ATM) Interconnect(異步傳輸模式互連器件) |
| 中文描述： | 異步轉(zhuǎn)移模式（ATM）的互連（異步傳輸模式互連器件） |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 125K |
| 代理商： | T8208 |
Product Brief
April 2000
13
CelXpres
T8206
Asynchronous Transfer Mode (ATM) Interconnect
Features
I
UTOPIA cell-level handshake interface (ATM or
PHY layers)
I
Multi-PHY (MPHY) operation
I
Programmable ATM layer supports up to 16 PHY
ports
I
Egress SDRAM buffer support to extend UTOPIA
output priority queues for 32K to 512K cells:
— 32 queues configurable up to four queues per
PHY with programmable sizes
— Programmable number of UTOPIA output
queues with four levels of priority
I
Support of ATM traffic management via partial
packet discard (PPD), forward explicit congestion
notification (FECN), and the cell loss priority (CLP)
bit
I
Controlled slew rate GTL+ I/O:
— Programmable as bus arbiter
— >1.5 Gbit/s cell bus operation
I
Flexible per virtual channel (VC) cell counters
I
Cell header insertion with virtual path identifier
(VPI) and virtual channel identifier (VCI) translation
via external SRAM (up to 64K entries)
I
Support of network node interface (NNI) and user
network interface (UNI) header types with optional
generic flow control (GFC) insertion
I
Programmable operations and maintenance and
resource management (OAM/RM) cell routing
I
Support of multicast and broadcast addresses per
PHY
I
Optional monitoring of misrouted cells
I
Microprocessor interface, supporting both Motor-
ola*
and Intel
modes (multiplexed and nonmulti-
plexed)
I
Control cell transmission and reception through
microprocessor port
I
Eight GPIO pins
I
JTAG support
I
Compatible with Transwitch
CellBus
I
Seamlessly extends WildWire central-site family
to the backplane
I
Single 3.3 V power supply
I
3.3 V TTL I/O (5 V tolerant)
I
272-pin plastic ball grid array (PBGA) package
I
Industrial temperature range (–40
°
C to +85
°
C)
Applications
I
Asymmetric digital subscriber line (ADSL) digital
subscriber line access multiplexers (DSLAMs)
I
Access gateways
I
Access multiplexers/concentrators
I
Multiservice platforms
Description
The CelXpresT8206 device meets the ATM Forum’s
universal test and operations PHY interface for ATM
(UTOPIA) Level 1, version 2.01 and Level 2, version
1.0 specifications for cell-level handshake and MPHY
data path operation. The T8206 supports MPHY
operation with one transmit cell available (TxCLAV)
signal and one receive cell available (RxCLAV) signal
for up to 16 PHY ports. In addition to the required
UTOPIA signals, the optional transmit parity
(TxPRTY) and receive parity (RxPRTY) signals are
provided.
* Motorolais a registered trademark of Motorola, Inc.
Intelis a registered trademark of Intel Corporation.
Transwitch and CellBus are registered trademark of Transwitch
Corp.
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