參數(shù)資料
型號(hào): T2316160A-60
廠商: TM Technology, Inc.
英文描述: SPST, Low Profile DIP Switches
中文描述: 1024K × 16動(dòng)態(tài)RAM快速頁面模式
文件頁數(shù): 1/13頁
文件大?。?/td> 139K
代理商: T2316160A-60
TE
CH
tm
DRAM
T2316160A
Taiwan Memory Technology, Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: APR. 2002
Revision:A
1024K x 16 DYNAMIC RAM
FAST PAGE MODE
FEATURES
Industry-standard x 16 pinouts and timing
functions.
Single 5V (
±
10%) power supply.
All device pins are TTL- compatible.
1K-cycle refresh in 16ms.
Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
BYTE WRITE and BYTE READ access cycles.
OPTION
TIMING
MARKING
45ns
-45
60ns
-60
PACKAGE
42-pin SOJ J
44/50-pin TSOPII S
GENERAL DESCRIPTION
The T2316160A is a randomly accessed solid state
memory containing 16,777,216 bits organized in a
x16 configuration. The T2316160A has both
BYTE WRITE and WORD WRITE access cycles
via two CAS pins. It offers Fast Page mode with
Extended Data Output.
The T2316160A CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high
during WRITE will result in a BYTE WRITE.
CASL to transition low in a WRITE cycle will
write data into the lower byte (DQ0~DQ7), and
CASH transiting low will write data into the
upper byte (DQ8~DQ15).
PIN ASSIGNMENT ( Top View )
DQ1
V
DD
46
45
44
43
41
42
40
36
35
34
33
32
31
30
29
1
2
3
4
6
5
7
8
9
11
15
16
17
18
19
20
DQ11
DQ10
DQ9
A8
A7
A9
10
21
22
47
48
49
50
DQ2
DQ3
A0
A1
DQ15
DQ14
DQ8
Vss
23
24
25
28
27
26
V
DD
DQ0
DQ4
DQ5
DQ6
DQ7
NC
NC
NC
WE
RAS
NC
NC
A2
A3
V
DD
DQ13
DQ12
Vss
NC
NC
OE
CASL
CASH
Vss
A6
A5
A4
40
39
38
37
35
36
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
6
5
7
8
9
11
12
13
14
15
16
17
18
19
20
10
21
41
42
22
DQ1
V
DD
DQ2
DQ3
A0
A1
V
DD
DQ0
DQ4
DQ5
DQ6
DQ7
NC
NC
WE
RAS
NC
NC
A2
A3
V
DD
DQ11
DQ10
DQ9
A8
A7
A9
DQ15
DQ14
DQ8
Vss
DQ13
DQ12
Vss
NC
OE
CASL
CASH
Vss
A6
A5
A4
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