參數(shù)資料
型號: STM32F103RB
廠商: 意法半導(dǎo)體
英文描述: Performance Line, ARM-based 32-bit MCU with Flash, USB, CAN,Seven 16-bit Timers, Two ADCs and Nine Communication interfaces(增強(qiáng)型,基于ARM內(nèi)核的32位 MCU,帶有Flash,USB,CAN,7個16位計時器,兩個ADC,兩個DAC和9個通信接口)
中文描述: 績效線,基于ARM的閃存,USB,加拿大,7 16 32位MCU位計時器,兩個ADC和9個通信接口(增強(qiáng)型,基于ARM的內(nèi)核的32位微控制器,帶有閃存,USB,加拿大,7個16位計時器,兩個模數(shù)轉(zhuǎn)換器,兩個DAC的和9個通信接口)
文件頁數(shù): 46/79頁
文件大小: 1124K
代理商: STM32F103RB
Electrical characteristics
STM32F103xx
5.3.11
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 31.
ESD absolute maximum ratings(1)
1.
TBD stands for to be determined.
Symbol
Ratings
Conditions
Class
Maximum value(2)
2.
Values based on characterization results, not tested in production.
Unit
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA = +25 °C
conforming to
JESD22-A114
2
2000
V
VESD(CDM)
Electrostatic discharge
voltage (charge device
model)
TA = +25 °C
conforming to
JESD22-C101
II
500
Table 32.
Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
II level A
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STM32F103RBH6TR 制造商:STMicroelectronics 功能描述:16/32-BITS MICROS - Tape and Reel
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