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參數(shù)資料
| 型號(hào)： | STLC7550TQFP |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW POWER LOW VOLTAGE ANALOG FRONT END |
| 中文描述： | 低電壓低功耗模擬前端 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 174K |
| 代理商： | STLC7550TQFP |
Sampling Period
1/2 Sampling Period (see Note)
FS
TxDI
HC1, HC0
1X
Data Word Input
Control Word
01
SCLK
TxDO
Data Word Output
Register Word
Note :
In slave mode, this 1/2 Sampling Period is not mandatory. If 1/2 Sampling Period is not provided, one sample is lost.
7
Figure 8 :
Mixed Mode
5 - HOST INTERFACE
The Host interface consist of the shift clock,
the frame synchronization signal, the ADC-
channel data output, and the DAC-channel
data input.
Two modes of serial transfer are available :
- First : Software mode for 15-bit transmit data
transfer and 16-bit receive data transfer
- Second : hardware mode for 16-bit data transfer.
FUNCTIONAL DESCRIPTION
(continued)
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
-
D15 D14
-
-
-
-
FS
SCLK
TxDI
HC1, HC0
Sampling period
00 or 01
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
-
D15 D14
-
-
-
-
TxDO
7
Figure 7 :
Data Mode
Both modes are selected by the Hardware Control
pins (HC0, HC1).
Table 2 :
Mode Selection
The data to the device, input/output are MSB-first
in 2’s complement format (see Table 2).
When Control Mode is selected, the device will
internally generate an additional Frame Synchroni-
zation Pulse (Secondary Frame Synchronization
Pulse) at the midpoint of the original Frame Period.
If the device is in slave mode the additional frame
sync (secondary frame sync pulse) must be gener-
ated by the processor. The Original Frame Syn-
chronization Pulse will also be referred to as the
Primary Frame Synchronization Pulse.
HC1
HC0
LSB
Useful Data
Secondary
FSYNC
No
Yes
No
Yes
Description
0
0
0
1
0
0
1
X
0
1
X
X
15bits
Software Mode for Data Transfer only.
Software Mode for Data Transfer + Control Register Transfer.
Hardware Mode for Data Transfer only.
Hardware Mode for Data Transfer + Control Register Transfer.
15bits (+16bits reg.)
16bits
16bits (+16bits reg.)
STLC7550
9/17
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